Abstract: A current source providing an output current with a fixed current range includes a bias circuit, a resistor, a current mirror, and a controller. The bias circuit provides a first voltage weighted with a first tunable coefficient and a second voltage weighted with a second tunable coefficient. The resistor has a tunable resistance for determining a bias current according to a voltage difference between the first and the second voltages and the tunable resistance. The current mirror generates the output current according to the bias current. The controller adjusts the tunable resistance and one of the first and the second tunable coefficients to achieve a voltage-current coefficient with different values, while the bias current and the output current are kept within a fixed current range.

Abstract: A memory device is disclosed that includes a plurality of word lines and a plurality of memory cells operating in one of a plurality of modes and coupled to at least one of the word lines. The memory device also includes a plurality of reference lines and reference cells. Each reference cell corresponds to one of the operating modes, supplies a reference current for the corresponding mode, and is coupled to at least one of the reference lines. A reference cell current from a reference cell can also be compared to a target range and, if outside the target range, the voltage level on a corresponding reference line can be adjusted accordingly such that the reference current falls within the target range (i.e., reference current trimming).

Abstract: In response to a disagreement between a previously generated check code associated with previously programmed data bits and a more recently generated check code generated in response to a read command, the comparison process is changed, between i) a value representing accessed data and ii) a reference applied to such accesses to distinguish between logical levels. For example, the ratio of resistances characterizing input circuits of a sense amplifier and/or the read bias arrangement and/or a read reference of a memory integrated circuit is/are changed.

Abstract: Source-side sensing techniques described herein determine the data value stored in a memory cell based on the difference in current between the read current from the source terminal of the memory cell and a sink current drawn from the read current. The sink current is drawn in response to the magnitude of a reference current provided by a reference current source such as a reference cell.

Abstract: A memory array is shown, including memory cells with source and drain doped regions, and global bit lines coupled to the doped regions via select transistors. The connections of the select transistors are configured such that the respective loading capacitances of two global bit lines respectively coupled to the source and the drain of a memory cell to be read do not vary with the memory cell to be read.

Abstract: According to an embodiment of the present invention, a method for detecting word line leakage in a memory device includes coupling a first word line in the memory device to a voltage source while coupling a second word line in the memory device to a ground level voltage. Next, the first word line is decoupled from the voltage source. The method also includes comparing a current of the first word line with a predetermined reference current for determining a leakage condition of the word line.

Abstract: Source-side sensing techniques described herein determine the data value stored in a memory cell based on the difference in current between the read current from the source terminal of the memory cell and a sink current drawn from the read current. The sink current is drawn in response to a magnitude of an operating voltage between first and second nodes. During a first time interval, the operating voltage is set in response to a magnitude of the reference current using a feedback path. During a second time interval following the first time interval, the operating voltage is held independent of the feedback path. The data value stored in the memory cell is determined based on a difference in current between the read current and the sink current during the second time interval.

Abstract: The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise.

Abstract: A memory array is shown, including memory cells with source and drain doped regions, and global bit lines coupled to the doped regions via select transistors. The connections of the select transistors are configured such that the respective loading capacitances of two global bit lines respectively coupled to the source and the drain of a memory cell to be read do not vary with the memory cell to be read. A method of operating the memory array is also shown, including, in reading a selected memory cell, applying voltages to the gate, the drain and the source thereof respectively from a word line, a first global bit line and a neighboring second global bit line, and turning on a select transistor coupled to a third global bit line separate from the first and the second ones by at least one other global bit line.

Abstract: A memory integrated circuit has an array of nonvolatile memory cells, bit lines accessing the array of nonvolatile memory cells, and bit line discharge circuitry. The bit lines have multiple discharge paths for a bit line at a same time, during a program operation.

Abstract: A memory and an operating method thereof are provided therein. When searching a boundary of a threshold voltage distribution of the memory, data errors resulted from tail bits of the memory would be corrected. Therefore, a sensing window could be broader, and the boundary of the threshold voltage distribution could be determined precisely.

Abstract: The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise.

Abstract: The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise.

Abstract: The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise.

Abstract: The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise.

Abstract: A Y-decoder includes a selection unit and a Y-MUX. The selection unit is coupled to the memory array for selecting the column lines. The Y-MUX is coupled to the selection unit for supplying a voltage to the selected column line. The Y-MUX includes a first switch, a second switch, a third switch and a fourth switch coupled in parallel. The first switch and the second switch are respectively for receiving a first shielding voltage and a second shielding voltage. The third switch and the fourth switch are respectively for receiving a first sensing voltage and a second sensing voltage.

Abstract: Provided is a MLC (Multi-level cell) memory device, comprising: a memory array, including a plurality of groups each storing a plurality of bits; and an inverse bit storage section, storing a first inverse bit data including a plurality of inverse bits, the plurality of bits in the same group in the memory array being related to a respective inverse bit.

Abstract: Source-side sensing techniques described herein determine the data value stored in a memory cell based on the difference in current between the read current from the source terminal of the memory cell and a sink current drawn from the read current. The sink current is drawn in response to the magnitude of a reference current provided by a reference current source such as a reference cell.

Abstract: Source-side sensing techniques described herein determine the data value stored in a memory cell based on the difference in current between the read current from the source terminal of the memory cell and a sink current drawn from the read current. The sink current is drawn in response to the magnitude of a reference current provided by a reference current source such as a reference cell.

Abstract: A memory and a boundary searching method thereof are provided therein. When searching a boundary of a threshold voltage distribution of the memory, data errors resulted from tail bits of the memory would be corrected. Therefore, a sensing window could be broader, and the boundary of the threshold voltage distribution could be determined precisely.