Patents by Inventor Han Wui Then

Han Wui Then has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12381039
    Abstract: High voltage metal insulator metal capacitors are described. In an example, a capacitor includes a first electrode plate, and a first capacitor dielectric on the first electrode plate. A second electrode plate is on the first capacitor dielectric and is over and parallel with the first electrode plate, and a second capacitor dielectric is on the second electrode plate. A third electrode plate is on the second capacitor dielectric and is over and parallel with the second electrode plate, and a third capacitor dielectric is on the third electrode plate. A fourth electrode plate is on the third capacitor dielectric and is over and parallel with the third electrode plate. In another example, a capacitor includes a first electrode, a capacitor dielectric on the first electrode, and a second electrode on the capacitor dielectric. The capacitor dielectric includes a plurality of alternating first dielectric layers and second dielectric layers.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: August 5, 2025
    Assignee: Intel Corporation
    Inventors: Han Wui Then, Marko Radosavljevic
  • Publication number: 20250231358
    Abstract: Gallium nitride (GaN) integrated circuit technology with optical communication is described. In an example, an integrated circuit structure includes a layer or substrate having a first region and a second region, the layer or substrate including gallium and nitrogen. A GaN-based device is in or on the first region of the layer or substrate. A CMOS-based device is over the second region of the layer or substrate. An interconnect structure is over the GaN-based device and over the CMOS-based device, the interconnect structure including conductive interconnects and vias in a dielectric layer. A photonics waveguide is over the interconnect structure, the photonics waveguide including silicon, and the photonics waveguide bonded to the dielectric layer of the interconnect structure.
    Type: Application
    Filed: April 4, 2025
    Publication date: July 17, 2025
    Inventors: Han Wui THEN, Marko RADOSAVLJEVIC, Nicole K. THOMAS, Pratik KOIRALA, Nityan NAIR, Paul B. FISCHER
  • Patent number: 12336268
    Abstract: Gallium nitride (GaN) integrated circuit technology is described. In an example, an integrated circuit structure includes a substrate including silicon, the substrate having a top surface. A first trench is in the substrate, the first trench having a first width. A second trench is in the substrate, the second trench having a second width less than the first width. A first island is in the first trench, the first island including gallium and nitrogen and having first corner facets below the top surface of the substrate. A second island is in the second trench, the second island including gallium and nitrogen and having second corner facets below the top surface of the substrate.
    Type: Grant
    Filed: August 13, 2021
    Date of Patent: June 17, 2025
    Assignee: Intel Corporation
    Inventors: Nicole K. Thomas, Samuel Bader, Marko Radosavljevic, Han Wui Then, Pratik Koirala, Nityan Nair
  • Patent number: 12302618
    Abstract: An integrated circuit structure includes a substrate including silicon, the substrate having a top surface. A first trench is in the substrate, the first trench having a first width and a first height. A second trench is in the substrate, the second trench having a second width and a second height. The second width is greater than the first width, and the second height is greater than the first height. A first island is in the first trench, the first island including gallium and nitrogen and having first corner facets at least partially below the top surface of the substrate. A second island is in the second trench, the second island including gallium and nitrogen and having second corner facets at least partially below the top surface of the substrate.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: May 13, 2025
    Assignee: Intel Corporation
    Inventors: Samuel James Bader, Pratik Koirala, Nicole K. Thomas, Han Wui Then, Marko Radosavljevic
  • Patent number: 12292608
    Abstract: Gallium nitride (GaN) integrated circuit technology with optical communication is described. In an example, an integrated circuit structure includes a layer or substrate having a first region and a second region, the layer or substrate including gallium and nitrogen. A GaN-based device is in or on the first region of the layer or substrate. A CMOS-based device is over the second region of the layer or substrate. An interconnect structure is over the GaN-based device and over the CMOS-based device, the interconnect structure including conductive interconnects and vias in a dielectric layer. A photonics waveguide is over the interconnect structure, the photonics waveguide including silicon, and the photonics waveguide bonded to the dielectric layer of the interconnect structure.
    Type: Grant
    Filed: September 15, 2021
    Date of Patent: May 6, 2025
    Assignee: Intel Corporation
    Inventors: Han Wui Then, Marko Radosavljevic, Nicole K. Thomas, Pratik Koirala, Nityan Nair, Paul B. Fischer
  • Publication number: 20250112210
    Abstract: Methods of selectively transferring integrated circuit (IC) components between substrates, and devices and systems formed using the same, are disclosed herein. In one embodiment, a first substrate with a release layer and a layer of IC components over the release layer is received, and a second substrate with one or more adhesive areas is received. The layer of IC components may include one or more transistors that contain one or more group III-V materials. The first substrate is partially bonded to the second substrate, such that a subset of IC components on the first substrate are bonded to the adhesive areas on the second substrate. The first substrate is then separated from the second substrate, and the subset of IC components bonded to the second substrate are separated from the first substrate and remain on the second substrate.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Han Wui Then, Adel Elsherbini, Feras Eid, Thomas L. Sounart, Georgios C. Dogiamis, Tushar Kanti Talukdar
  • Publication number: 20250105053
    Abstract: Methods of selectively transferring integrated circuit (IC) components between substrates, and devices and systems formed using the same, are disclosed herein. In one embodiment, a first substrate with a release layer and a layer of IC components over the release layer is received, and a second substrate with one or more adhesive areas is received. The layer of IC components may include one or more waveguides, ring resonators, drivers, photodetectors, transimpedance amplifiers, and/or electronic integrated circuits. The first substrate is partially bonded to the second substrate, such that a subset of IC components on the first substrate are bonded to the adhesive areas on the second substrate. The first substrate is then separated from the second substrate, and the subset of IC components bonded to the second substrate are separated from the first substrate and remain on the second substrate.
    Type: Application
    Filed: September 25, 2023
    Publication date: March 27, 2025
    Applicant: Intel Corporation
    Inventors: Adel Elsherbini, Han Wui Then, Feras Eid, James E. Jaussi, Ganesh Balamurugan, Thomas L. Sounart, Johanna Swan, Henning Braunisch, Tushar Kanti Talukdar, Shawna M. Liff
  • Publication number: 20250079292
    Abstract: Embodiments of the invention include a microelectronic device that includes a substrate, at least one dielectric layer on the substrate and a plurality of conductive lines within the at least one dielectric layer. The microelectronic device also includes an air gap structure that is located below two or more of the plurality of conductive lines.
    Type: Application
    Filed: November 18, 2024
    Publication date: March 6, 2025
    Applicant: Tahoe Research, Ltd.
    Inventors: Han Wui THEN, Sansaptak DASGUPTA, Marko RADOSAVLJEVIC, Sanaz K. GARDNER
  • Publication number: 20250040231
    Abstract: Gallium nitride (GaN) three-dimensional integrated circuit technology is described. In an example, an integrated circuit structure includes a layer including gallium and nitrogen, a plurality of gate structures over the layer including gallium and nitrogen, a source region on a first side of the plurality of gate structures, a drain region on a second side of the plurality of gate structures, the second side opposite the first side, and a drain field plate above the drain region wherein the drain field plate is coupled to the source region. In another example, a semiconductor package includes a package substrate. A first integrated circuit (IC) die is coupled to the package substrate. The first IC die includes a GaN device layer and a Si-based CMOS layer.
    Type: Application
    Filed: October 14, 2024
    Publication date: January 30, 2025
    Inventors: Han Wui THEN, Marko RADOSAVLJEVIC, Pratik KOIRALA, Nicole K. THOMAS, Paul B. FISCHER, Adel A. ELSHERBINI, Tushar TALUKDAR, Johanna M. SWAN, Wilfred GOMES, Robert S. CHAU, Beomseok CHOI
  • Patent number: 12199018
    Abstract: Disclosed herein are microelectronic assemblies including direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first subregion and a second subregion, and the first subregion has a greater metal density than the second subregion. In some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first metal contact and a second metal contact, the first metal contact has a larger area than the second metal contact, and the first metal contact is electrically coupled to a power/ground plane of the first microelectronic component.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: January 14, 2025
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Krishna Bharath, Han Wui Then, Kimin Jun, Aleksandar Aleksov, Mohammad Enamul Kabir, Shawna M. Liff, Johanna M. Swan, Feras Eid
  • Patent number: 12156473
    Abstract: Disclosed herein are inductor/core assemblies for integrated circuits (ICs), as well as related structures, methods, and devices. In some embodiments, an IC structure may include an inductor and a magnetic core in an interior of the inductor. The magnetic core may be movable perpendicular to a plane of the inductor.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: November 26, 2024
    Assignee: Intel Corporation
    Inventors: Kevin L. Lin, Nicholas James Harold McKubre, Han Wui Then
  • Patent number: 12148757
    Abstract: Disclosed herein are IC structures, packages, and devices that include Si-based semiconductor material stack monolithically integrated on the same support structure as non-Si transistors or other non-Si-based devices. In some aspects, the Si-based semiconductor material stack may be provided by semiconductor regrowth over an insulator material. Providing a Si-based semiconductor material stack monolithically integrated on the same support structure as non-Si based devices may provide a viable approach to integrating Si-based transistors with non-Si technologies because the Si-based semiconductor material stack may serve as a foundation for forming Si-based transistors.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: November 19, 2024
    Assignee: Intel Corporation
    Inventors: Nidhi Nidhi, Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta, Paul B. Fischer, Rahul Ramaswamy, Walid M. Hafez, Johann Christian Rode
  • Patent number: 12148690
    Abstract: Embodiments of the invention include a microelectronic device that includes a substrate, at least one dielectric layer on the substrate and a plurality of conductive lines within the at least one dielectric layer. The microelectronic device also includes an air gap structure that is located below two or more of the plurality of conductive lines.
    Type: Grant
    Filed: February 17, 2023
    Date of Patent: November 19, 2024
    Assignee: Tahoe Research, Ltd.
    Inventors: Han Wui Then, Sansaptak Dasgupta, Marko Radosavljevic, Sanaz K. Gardner
  • Patent number: 12148747
    Abstract: Gallium nitride (GaN) three-dimensional integrated circuit technology is described. In an example, an integrated circuit structure includes a layer including gallium and nitrogen, a plurality of gate structures over the layer including gallium and nitrogen, a source region on a first side of the plurality of gate structures, a drain region on a second side of the plurality of gate structures, the second side opposite the first side, and a drain field plate above the drain region wherein the drain field plate is coupled to the source region. In another example, a semiconductor package includes a package substrate. A first integrated circuit (IC) die is coupled to the package substrate. The first IC die includes a GaN device layer and a Si-based CMOS layer.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: November 19, 2024
    Assignee: Intel Corporation
    Inventors: Han Wui Then, Marko Radosavljevic, Pratik Koirala, Nicole K. Thomas, Paul B. Fischer, Adel A. Elsherbini, Tushar Talukdar, Johanna M. Swan, Wilfred Gomes, Robert S. Chau, Beomseok Choi
  • Publication number: 20240355768
    Abstract: Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes at least part of an inductor.
    Type: Application
    Filed: July 2, 2024
    Publication date: October 24, 2024
    Applicant: Intel Corporation
    Inventors: Adel A. Elsherbini, Krishna Bharath, Kevin P. O'Brien, Kimin Jun, Han Wui Then, Mohammad Enamul Kabir, Gerald S. Pasdast, Feras Eid, Aleksandar Aleksov, Johanna M. Swan, Shawna M. Liff
  • Patent number: 12125888
    Abstract: A device including a III-N material is described. In an example, the device has terminal structure having a first group III-Nitride (III-N) material. The terminal structure has a central body and a first plurality of fins, and a second plurality of fins, opposite the first plurality of fins. A polarization charge inducing layer is above a first portion of the central body. A gate electrode is above the polarization charge inducing layer. The device further includes a source structure and a drain structure, each including impurity dopants, on opposite sides of the gate electrode and on the plurality of fins, and a source contact on the source structure and a drain contact on the drain structure.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: October 22, 2024
    Assignee: Intel Corporation
    Inventors: Marko Radosavljevic, Han Wui Then, Sansaptak Dasgupta
  • Patent number: 12107060
    Abstract: Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes at least part of an inductor.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: October 1, 2024
    Assignee: Intel Corproation
    Inventors: Adel A. Elsherbini, Zhiguo Qian, Gerald S. Pasdast, Mohammad Enamul Kabir, Han Wui Then, Kimin Jun, Kevin P. O'Brien, Johanna M. Swan, Shawna M. Liff, Aleksandar Aleksov, Feras Eid
  • Patent number: 12080763
    Abstract: A transistor includes a polarization layer above a channel layer including a first III-Nitride (III-N) material, a gate electrode above the polarization layer, a source structure and a drain structure on opposite sides of the gate electrode, where the source structure and a drain structure each include a second III-N material. The transistor further includes a silicide on at least a portion of the source structure or the drain structure. A contact is coupled through the silicide to the source or drain structure.
    Type: Grant
    Filed: May 26, 2022
    Date of Patent: September 3, 2024
    Assignee: Intel Corporation
    Inventors: Sansaptak Dasgupta, Marko Radosavljevic, Han Wui Then, Paul Fischer, Walid Hafez
  • Patent number: 12062631
    Abstract: Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes at least part of an inductor.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: August 13, 2024
    Assignee: Intel Corporation
    Inventors: Adel A Elsherbini, Krishna Bharath, Kevin P. O'Brien, Kimin Jun, Han Wui Then, Mohammad Enamul Kabir, Gerald S. Pasdast, Feras Eid, Aleksandar Aleksov, Johanna M. Swan, Shawna M. Liff
  • Patent number: 12034085
    Abstract: A variable capacitance III-N device having multiple two-dimensional electron gas (2DEG) layers are described. In some embodiments, the device comprises a first source and a first drain; a first polarization layer adjacent to the first source and the first drain; a first channel layer coupled to the first source and the first drain and adjacent to the first polarization layer, the first channel layer comprising a first 2DEG region; a second source and a second drain; a second polarization layer adjacent to the second source and the second drain; and a second channel layer coupled to the second source and the second drain and adjacent to the second polarization layer, the second channel layer comprising a second 2DEG region, wherein the second channel layer is over the first polarization layer.
    Type: Grant
    Filed: June 23, 2022
    Date of Patent: July 9, 2024
    Assignee: Intel Corporation
    Inventors: Harald Gossner, Peter Baumgartner, Uwe Hodel, Domagoj Siprak, Stephan Leuschner, Richard Geiger, Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta