Abstract: An integrated circuit structure comprises a first dielectric layer disposed above a substrate. The integrated circuit structure comprises an interconnect structure comprising a first interconnect on a first metal layer, a second interconnect on a second metal layer, and a via connecting the first interconnect and the second interconnect, the first interconnect being on or within the first dielectric layer. A metal-insulator-metal (MIM) capacitor is formed in or on the first dielectric layer in the first metal layer adjacent to the interconnect structure. The MIM capacitor comprises a bottom electrode plate comprising a first low resistivity material, an insulator stack on the bottom electrode plate, the insulator stack comprising at least one of an etch stop layer and a high-K dielectric layer; and a top electrode plate on the insulator stack, the top electrode plate comprising a second low resistivity material.

Abstract: A transistor includes a polarization layer above a channel layer including a first III-Nitride (III-N) material, a gate electrode above the polarization layer, a source structure and a drain structure on opposite sides of the gate electrode, where the source structure and a drain structure each include a second III-N material. The transistor further includes a silicide on at least a portion of the source structure or the drain structure. A contact is coupled through the silicide to the source or drain structure.

Abstract: Transistor structures including a fin structure having multiple graded III-N material layers with polarization layers therebetween, integrated circuits including such transistor structures, and methods for forming the transistor structures are discussed. The transistor structures further include a source, a drain, and a gate coupled to the fin structure. The fin structure provides a multi-gate multi-nanowire confined transistor architecture.

Abstract: Group-III nitride (III-N) tunnel devices with a device structure including multiple quantum wells. A bias voltage applied across first device terminals may align the band structure to permit carrier tunneling between a first carrier gas residing in a first of the wells to a second carrier gas residing in a second of the wells. A III-N tunnel device may be operable as a diode, or further include a gate electrode. The III-N tunnel device may display a non-linear current-voltage response with negative differential resistance, and be employed as a frequency mixer operable in the GHz and THz bands. In some examples, a GHz-THz input RF signal and local oscillator signal are coupled into a gate electrode of a III-N tunnel device biased within a non-linear regime to generate an output RF signal indicative of a frequency difference between the RF signal and a local oscillator signal.

Abstract: Integrated circuit architectures for load and input matching that include a capacitance selectable between a plurality of discrete levels, which are associated with a number of field effect transistors (FET) capacitor structures that are in an on-state. The capacitance comprises a metal-oxide-semiconductor (MOS) capacitance associated with each of the FET capacitor structures, and may be selectable through application of a bias voltage applied between a first circuit node and a second circuit node. Gate electrodes of the FET capacitor structures may be coupled in electrical parallel to the first circuit node, while source/drains of the FET capacitor structures are coupled in electrical parallel to the second circuit node. Where the FET capacitor structures have different gate-source threshold voltages, the number of FET capacitor structures in the on-state may be varied according to the bias voltage, and the capacitance correspondingly tuned to a desired value.

Abstract: A variable capacitance III-N device having multiple two-dimensional electron gas (2DEG) layers are described. In some embodiments, the device comprises a first source and a first drain; a first polarization layer adjacent to the first source and the first drain; a first channel layer coupled to the first source and the first drain and adjacent to the first polarization layer, the first channel layer comprising a first 2DEG region; a second source and a second drain; a second polarization layer adjacent to the second source and the second drain; and a second channel layer coupled to the second source and the second drain and adjacent to the second polarization layer, the second channel layer comprising a second 2DEG region, wherein the second channel layer is over the first polarization layer.

Abstract: A Group III-Nitride (III-N) device structure is presented comprising: a heterostructure having three or more layers comprising III-N material, a cathode comprising donor dopants, wherein the cathode is on a first layer of the heterostructure, an anode within a recess that extends through two or more of the layers of the heterostructure, wherein the anode comprises a first region wherein the anode is separated from the heterostructure by a high k dielectric material, and a second region wherein the anode is in direct contact with the heterostructure, and a conducting region in the first layer in direct contact to the cathode and conductively connected to the anode. Other embodiments are also disclosed and claimed.

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first microelectronic component, having a first surface and an opposing second surface including a first direct bonding region at the second surface with first metal contacts and a first dielectric material between adjacent ones of the first metal contacts; a second microelectronic component, having a first surface and an opposing second surface, including a second direct bonding region at the first surface with second metal contacts and a second dielectric material between adjacent ones of the second metal contacts, wherein the second microelectronic component is coupled to the first microelectronic component by the first and second direct bonding regions; and a shield structure in the first direct bonding dielectric material at least partially surrounding the one or more of the first metal contacts.

Abstract: A substrate contact diode is disclosed. The substrate contact includes a first type substrate implant tap in a substrate, a second type epitaxial implant in an epitaxial layer that is on the substrate, and a first type epitaxial region above the second type epitaxial implant. A contact electrode that extends upward from the top of the first type epitaxial region to the surface of an interlayer dielectric that surrounds the contact electrode.

Abstract: A method for forming non-planar capacitors of desired dimensions is disclosed. The method is based on providing a three-dimensional structure of a first material over a substrate, enclosing the structure with a second material that is sufficiently etch-selective with respect to the first material, and then performing a wet etch to remove most of the first material but not the second material, thus forming a cavity within the second material. Shape and dimensions of the cavity are comparable to those desired for the final non-planar capacitor. At least one electrode of a capacitor may then be formed within the cavity. Using the etch selectivity of the first and second materials advantageously allows applying wet etch techniques for forming high aspect ratio openings in fabricating non-planar capacitors, which is easier and more reliable than relying on dry etch techniques.

Abstract: Diodes employing one or more Group III-Nitride polarization junctions. A III-N polarization junction may include two III-N material layers having opposite crystal polarities. The opposing polarities may induce a two-dimensional charge sheet (e.g., 2D electron gas) within each of the two III-N material layers. Opposing crystal polarities may be induced through introduction of an intervening layer between two III-N material layers. The intervening layer may be of a material other than a Group III-Nitride. Where a P-i-N diode structure includes two Group III-Nitride polarization junctions, opposing crystal polarities at a first of such junctions may induce a 2D electron gas (2DEG), while opposing crystal polarities at a second of such junctions may induce a 2D hole gas (2DHG). Diode terminals may then couple to each of the 2DEG and 2DHG.

Abstract: Techniques related to III-N transistors having improved performance, systems incorporating such transistors, and methods for forming them are discussed. Such transistors include first and second crystalline III-N material layers separated by an intervening layer other than a III-N material such that the first crystalline III-N material layer has a first crystal orientation that is inverted with respect to a second crystal orientation of the second crystalline III-N material layer.

Abstract: A diode is disclosed. The diode includes a semiconductor substrate, a hard mask formed above the substrate, vertically oriented components of a first material adjacent sides of the hard mask, and laterally oriented components of the first material on top of the hard mask. The laterally oriented components are oriented in a first direction and a second direction. The diode also includes a second material on top of the first material. The second material forms a Schottky barrier.

Abstract: Disclosed herein are integrated circuit (IC) components with substrate cavities, as well as related techniques and assemblies. In some embodiments, an IC component may include a substrate, a device layer on the substrate, a plurality of interconnect layers on the device layer, and a cavity in the substrate.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate, an epitaxial layer on the substrate, a semiconductor interlayer on top of the epitaxial layer, a gate conductor above the semiconductor interlayer, a gate insulator on the bottom and sides of the gate conductor and contacting the top surface of the semiconductor interlayer, a source region extending into the epitaxial layer, and a drain region extending into the epitaxial layer. The semiconductor device also includes a first polarization layer on the semiconductor interlayer between the source region and the gate conductor and a second polarization layer on the semiconductor interlayer between the drain region and the gate conductor.

Abstract: A device including a III-N material is described. In an example, a device includes a first layer including a first group III-nitride (III-N) material and a polarization charge inducing layer, including a second III-N material, above the first layer. The device further includes a gate electrode above the polarization charge inducing layer and a source structure and a drain structure on opposite sides of the gate electrode. The source structure and the drain structure both include a first portion adjacent to the first layer and a second portion above the first portion, the first portion includes a third III-N material with an impurity dopant, and the second portion includes a fourth III-N material, where the fourth III-N material includes the impurity dopant and further includes indium, where the indium content increases with distance from the first portion.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate, a superlattice that includes a plurality of layers of alternating materials above the substrate, where each of the plurality of layers corresponds to a threshold voltage, a gate trench extending into the superlattice to a predetermined one of the plurality of layers of the superlattice structure, and a high-k layer on the bottom and sidewall of the trench, the high-k layer contacting an etch stop layer of one of the plurality of layers of alternating materials. A gate is located in the trench on top of the high-k layer.

Abstract: Techniques are disclosed for forming high frequency film bulk acoustic resonator (FBAR) devices using epitaxially grown piezoelectric films. In some cases, the piezoelectric layer of the FBAR may be an epitaxial III-V layer such as an aluminum nitride (AlN) or other group III material-nitride (III-N) compound film grown as a part of a III-V material stack, although any other suitable piezoelectric materials can be used. Use of an epitaxial piezoelectric layer in an FBAR device provides numerous benefits, such as being able to achieve films that are thinner and higher quality compared to sputtered films, for example. The higher quality piezoelectric film results in higher piezoelectric coupling coefficients, which leads to higher Q-factor of RF filters including such FBAR devices. Therefore, the FBAR devices can be included in RF filters to enable filtering high frequencies of greater than 3 GHz, which can be used for 5G wireless standards, for example.

Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device that may include an III-V transistor with a resistive gate contact. A semiconductor device may include a substrate, and a channel base including a layer of GaN above the substrate. A channel stack may be above the channel base, and may include a layer of GaN in the channel stack, and a polarization layer above the layer of GaN in the channel stack. A gate stack may be above the channel stack, where the gate stack may include a gate dielectric layer above the channel stack, and a resistive gate contact above the gate dielectric layer. The resistive gate contact may include silicon (Si) or germanium (Ge). Other embodiments may be described and/or claimed.

Abstract: Techniques related to III-N transistors having improved performance, systems incorporating such transistors, and methods for forming them are discussed. Such transistors include first and second crystalline III-N material layers separated by an intervening layer other than a III-N material such that the first crystalline III-N material layer has a first crystal orientation that is inverted with respect to a second crystal orientation of the second crystalline III-N material layer.