Abstract: Gallium nitride (GaN) three-dimensional integrated circuit technology is described. In an example, an integrated circuit structure includes a layer including gallium and nitrogen, a plurality of gate structures over the layer including gallium and nitrogen, a source region on a first side of the plurality of gate structures, a drain region on a second side of the plurality of gate structures, the second side opposite the first side, and a drain field plate above the drain region wherein the drain field plate is coupled to the source region. In another example, a semiconductor package includes a package substrate. A first integrated circuit (IC) die is coupled to the package substrate. The first IC die includes a GaN device layer and a Si-based CMOS layer.

Abstract: Gallium nitride (GaN) three-dimensional integrated circuit technology is described. In an example, an integrated circuit structure includes a layer including gallium and nitrogen, a plurality of gate structures over the layer including gallium and nitrogen, a source region on a first side of the plurality of gate structures, a drain region on a second side of the plurality of gate structures, the second side opposite the first side, and a drain field plate above the drain region wherein the drain field plate is coupled to the source region. In another example, a semiconductor package includes a package substrate. A first integrated circuit (IC) die is coupled to the package substrate. The first IC die includes a GaN device layer and a Si-based CMOS layer.

Abstract: Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes at least part of an inductor.

Abstract: Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes at least part of an inductor.

Abstract: Embodiments disclosed herein include resonators and methods of forming such resonators. In an embodiment a resonator comprises a substrate, where a cavity is disposed into a surface of the substrate, and a piezoelectric film suspended over the cavity. In an embodiment, the piezoelectric film has a first surface and a second surface opposite from the first surface, and the piezoelectric film is single crystalline and has a thickness that is 0.5 ?m or less. In an embodiment a first electrode is over the first surface of the piezoelectric film, and a second electrode is over the second surface of the piezoelectric film.

Abstract: Disclosed herein are microelectronic assemblies including direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first subregion and a second subregion, and the first subregion has a greater metal density than the second subregion. In some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first metal contact and a second metal contact, the first metal contact has a larger area than the second metal contact, and the first metal contact is electrically coupled to a power/ground plane of the first microelectronic component.

Abstract: Co-integrated gallium nitride (GaN) complementary metal oxide semiconductor (CMOS) integrated circuit technology is described. In an example, a semiconductor structure includes a silicon (111) substrate having a first region and a second region. A structure including gallium and nitrogen is on the first region of the silicon (111) substrate, the structure including gallium and nitrogen having a top surface. A structure including germanium is on the second region of the silicon (111) substrate, the structure including germanium having a top surface co-planar with the top surface of the structure including gallium and nitrogen. A dielectric spacer is laterally between and in contact with the structure including gallium and nitrogen and the structure including germanium, the dielectric spacer on the silicon (111) substrate.

Abstract: Methods and apparatus to form silicon-based transistors on group III-nitride materials using aspect ratio trapping are disclosed. An example integrated circuit includes a group III-nitride substrate and a fin of silicon formed on the group III-nitride substrate. The integrated circuit further includes a first transistor formed on the fin of silicon and a second transistor formed on the group III-nitride substrate.

Abstract: Light emitting devices employing one or more Group III-Nitride polarization junctions. A III-N polarization junction may include two III-N material layers having opposite crystal polarities. The opposing polarities may induce a two-dimensional charge carrier sheet within each of the two III-N material layers. Opposing crystal polarities may be induced through introduction of an intervening material layer between two III-N material layers. Where a light emitting structure includes a quantum well (QW) structure between two Group III-Nitride polarization junctions, a 2D electron gas (2DEG) induced at a first polarization junction and/or a 2D hole gas (2DHG) induced at a second polarization junction on either side of the QW structure may supply carriers to the QW structure. An improvement in quantum efficiency may be achieved where the intervening material layer further functions as a barrier to carrier recombination outside of the QW structure.

Abstract: Disclosed herein are IC structures, packages, and devices that include linearization devices integrated on the same support structure as III-N transistors. A linearization device may be any suitable device that may exhibit behavior complementary to that of a III-N transistor so that a combined behavior of the III-N transistor and the linearization device includes less nonlinearity than the behavior of the III-N transistor alone. Linearization devices may be implemented as, e.g., one-sided diodes, two-sided diodes, or P-type transistors. Integrating linearization devices on the same support structure with III-N transistors advantageously provides an integrated solution based on III-N transistor technology, thus providing a viable approach to reducing or eliminating nonlinear behavior of III-N transistors.

Abstract: A device including a III-N material is described. In an example, the device has a terminal structure with a central body and a first plurality of fins, and a second plurality of fins, opposite the first plurality of fins. A polarization charge inducing layer including a III-N material in the terminal structure. A gate electrode is disposed above and on a portion of the polarization charge inducing layer. A source structure is on the polarization charge inducing layer and on sidewalls of the first plurality of fins. A drain structure is on the polarization charge inducing layer and on sidewalls of the second plurality of fins. The device further includes a source structure and a drain structure on opposite sides of the gate electrode and a source contact on the source structure and a drain contact on the drain structure.

Abstract: A device including a III-N material is described. In an example, the device has a terminal structure with a central body and a first plurality of fins, and a second plurality of fins, opposite the first plurality of fins. A polarization charge inducing layer including a III-N material in the terminal structure. A gate electrode is disposed above and on a portion of the polarization charge inducing layer. A source structure is on the polarization charge inducing layer and on sidewalls of the first plurality of fins. A drain structure is on the polarization charge inducing layer and on sidewalls of the second plurality of fins. The device further includes a source structure and a drain structure on opposite sides of the gate electrode and a source contact on the source structure and a drain contact on the drain structure.

Abstract: Methods and apparatus to form silicon-based transistors on group III-nitride materials using aspect ratio trapping are disclosed. An example integrated circuit includes a group III-nitride substrate and a fin of silicon formed on the group III-nitride substrate. The integrated circuit further includes a first transistor formed on the fin of silicon and a second transistor formed on the group III-nitride substrate.

Abstract: Techniques are disclosed for forming integrated circuit film bulk acoustic resonator (FBAR) devices having multiple resonator thicknesses on a common substrate. A piezoelectric stack is formed in an STI trench and overgrown onto the STI material. In some cases, the piezoelectric stack can include epitaxially grown AlN. In some cases, the piezoelectric stack can include single crystal (epitaxial) AlN in combination with polycrystalline (e.g., sputtered) AlN. The piezoelectric stack thus forms a central portion having a first resonator thickness and end wings extending from the central portion and having a different resonator thickness. Each wing may also have different thicknesses from one another. Thus, multiple resonator thicknesses can be achieved on a common substrate, and hence, multiple resonant frequencies on that same substrate. The end wings can have metal electrodes formed thereon, and the central portion can have a plurality of IDT electrodes patterned thereon.

Abstract: Embodiments disclosed herein comprise a high electron mobility transistor (HEMT). In an embodiment, the HEMT comprises a heterojunction channel that includes a first semiconductor layer and a second semiconductor layer over the first semiconductor layer. In an embodiment a first interface layer is between the first semiconductor layer and the second semiconductor layer, and a second interface layer is over the first interface layer. In an embodiment, the HEMT further comprises a source contact, a drain contact, and a gate contact between the source contact and the drain contact.

Abstract: Techniques are disclosed for forming a heterojunction bipolar transistor (HBT) that includes a laterally grown epitaxial (LEO) base layer that is disposed between corresponding emitter and collector layers. Laterally growing the base layer of the HBT improves electrical and physical contact between electrical contacts to associated portions of the HBT device (e.g., a collector). By improving the quality of electrical and physical contact between a layer of an HBT device and corresponding electrical contacts, integrated circuits using HBTs are better able to operate at gigahertz frequency switching rates used for modern wireless communications.

Abstract: Techniques are disclosed for gallium nitride (GaN) oxide isolation and formation of GaN transistor structures on a substrate. In some cases, the GaN transistor structures can be used for system-on-chip integration of high-voltage GaN front-end radio frequency (RF) switches on a bulk silicon substrate. The techniques can include, for example, forming multiple fins in a substrate, depositing the GaN layer on the fins, oxidizing at least a portion of each fin in a gap below the GaN layer, and forming one or more transistors on and/or from the GaN layer. In some cases, the GaN layer is a plurality of GaN islands, each island corresponding to a given fin. The techniques can be used to form various non-planar isolated GaN transistor architectures having a relatively small form factor, low on-state resistance, and low off-state leakage, in some cases.

Abstract: A device including a III-N material is described. In an example, the device has terminal structure having a first group III-Nitride (III-N) material. The terminal structure has a central body and a first plurality of fins, and a second plurality of fins, opposite the first plurality of fins. A polarization charge inducing layer is above a first portion of the central body. A gate electrode is above the polarization charge inducing layer. The device further includes a source structure and a drain structure, each including impurity dopants, on opposite sides of the gate electrode and on the plurality of fins, and a source contact on the source structure and a drain contact on the drain structure.

Abstract: Light emitting devices employing one or more Group III-Nitride polarization junctions. A III-N polarization junction may include two III-N material layers having opposite crystal polarities. The opposing polarities may induce a two-dimensional charge carrier sheet within each of the two III-N material layers. Opposing crystal polarities may be induced through introduction of an intervening material layer between two III-N material layers. Where a light emitting structure includes a quantum well (QW) structure between two Group III-Nitride polarization junctions, a 2D electron gas (2DEG) induced at a first polarization junction and/or a 2D hole gas (2DHG) induced at a second polarization junction on either side of the QW structure may supply carriers to the QW structure. An improvement in quantum efficiency may be achieved where the intervening material layer further functions as a barrier to carrier recombination outside of the QW structure.

Abstract: III-N semiconductor heterostructures on III-N epitaxial islands laterally overgrown from a mesa of a silicon substrate. An IC may include a III-N semiconductor device disposed on the III-N epitaxial island overhanging the silicon mesa and may further include a silicon-based MOSFET monolithically integrated with the III-N device. Lateral epitaxial overgrowth from silicon mesas may provide III-N semiconductor regions of good crystal quality upon which transistors or other active semiconductor devices may be fabricated. Overhanging surfaces of III-N islands may provide multiple device layers on surfaces of differing polarity. Spacing between separate III-N islands may provide mechanical compliance to an IC including III-N semiconductor devices. Undercut of the silicon mesa may be utilized for transfer of III-N epitaxial islands to alternative substrates.