Abstract: A lateral diffusion metal oxide semiconductor (LDMOS) device includes a first fin-shaped structure on a substrate, a shallow trench isolation (STI) adjacent to the first fin-shaped structure, a first gate structure on the first fin-shaped structure, a spacer adjacent to the first gate structure, and a contact field plate adjacent to the first gate structure and directly on the STI. Preferably, a sidewall of the spacer is aligned with a sidewall of the first fin-shaped structure.

Abstract: A lateral diffusion metal oxide semiconductor (LDMOS) device includes a first fin-shaped structure on a substrate, a shallow trench isolation (STI) adjacent to the first fin-shaped structure, a first gate structure on the first fin-shaped structure, a spacer adjacent to the first gate structure, and a contact field plate adjacent to the first gate structure and directly on the STI. Preferably, a sidewall of the spacer is aligned with a sidewall of the first fin-shaped structure.

Abstract: A lift pin includes a lift pin body arranged along a lift pin axis having a contact pad, a stem segment, a neck segment, and a span feature. The contact pad is defined at a first end of the lift pin body, the stem segment extends from the contact pad, and the neck segment extends from the stem segment. The span feature is defined at a second end of the lift pin body, is connected to the contact pad by the neck segment and the stem segment, and has a minor and major widths. The minor width is equivalent to a neck diameter defined by the neck segment, the major with is greater than the minor width, and the major width is greater than a stem diameter defined by the stem segment. Lift pin arrangements, semiconductor processing systems, and methods of making semiconductor processing systems are also described.

Abstract: A shaft member includes a cylindrical body formed from a ceramic material and having a drive segment, a frustoconical segment, and an end key segment. The drive segment extends about a rotation axis, the frustoconical segment is offset from the drive segment along the rotation axis, and the end key segment extends axially from the frustoconical segment and is axially separated from the drive segment by the frustoconical segment of the shaft member. The end key segment has a first circumferential facet and a second circumferential facet circumferentially opposite the first circumferential facet to fix the shaft member in rotation about the rotation axis relative to a support member seated when the end key segment is slidably received within an end key socket defined within the support member. Process kits, semiconductor processing systems, and methods of making semiconductor processing systems are also described.

Abstract: A chamber arrangement includes a chamber body, a substrate support, and a laser source. The substrate support is arranged within the chamber body and supported for rotation about a rotation axis relative to the chamber body. The laser source is arranged outside of the chamber body and optically coupled to the substrate support along a lasing axis. The lasing axis intersects the substrate support at a location radially outward from an outer periphery of a substrate seated on the substrate support. A semiconductor processing system and a material layer deposition method are also described.

Abstract: Methods, systems, and assemblies suitable for gas-phase processes are disclosed. An exemplary assembly includes a susceptor ring and at least one injector tube. The injector tube can be disposed within the susceptor ring to provide a gas to a peripheral region of a substrate. Methods, systems, and assemblies can be used to obtain desired (e.g. composition and/or thickness) profiles of material on a substrate surface.

Abstract: Methods, systems, and assemblies suitable for gas-phase processes are disclosed. An exemplary assembly includes a susceptor ring and at least one injector tube. The injector tube can be disposed within the susceptor ring to provide a gas to a lower chamber area of a reactor. Methods, systems, and assemblies can be used to obtain desired etching and purging of the lower chamber area.

Abstract: A lateral diffusion metal oxide semiconductor (LDMOS) device includes a first fin-shaped structure on a substrate, a shallow trench isolation (STI) adjacent to the first fin-shaped structure, a first gate structure on the first fin-shaped structure, a spacer adjacent to the first gate structure, and a contact field plate adjacent to the first gate structure and directly on the STI. Preferably, a sidewall of the spacer is aligned with a sidewall of the first fin-shaped structure.

Abstract: A method for fabricating a lateral diffusion metal oxide semiconductor (LDMOS) device includes the steps of first forming a first fin-shaped structure and a second fin-shaped structure on a substrate, forming a shallow trench isolation (STI) between the first fin-shaped structure and the second fin-shaped structure, forming a first gate structure on the first fin-shaped structure and a second gate structure on the second fin-shaped structure, forming a source region on the first fin-shaped structure, forming a drain region on the second fin-shaped structure, and forming a contact field plate directly on the STI.

Abstract: A power semiconductor device includes a substrate, a first well, a second well, a drain, a source, a first gate structure, a second gate structure and a doping region. The first well has a first conductivity and extends into the substrate from a substrate surface. The second well has a second conductivity and extends into the substrate from the substrate surface. The drain has the first conductivity and is disposed in the first well. The source has the first conductivity and is disposed in the second well. The first gate structure is disposed on the substrate surface and at least partially overlapping with the first well and second well. The second gate structure is disposed on the substrate surface and overlapping with the second well. The doping region has the first conductivity, is disposed in the second well and connects the first gate structure with the second gate structure.

Abstract: A method for fabricating a lateral diffusion metal oxide semiconductor (LDMOS) device includes the steps of first forming a first fin-shaped structure and a second fin-shaped structure on a substrate, forming a shallow trench isolation (STI) between the first fin-shaped structure and the second fin-shaped structure, forming a first gate structure on the first fin-shaped structure and a second gate structure on the second fin-shaped structure, forming a source region on the first fin-shaped structure, forming a drain region on the second fin-shaped structure, and forming a contact field plate directly on the STI.

Abstract: A method of operating a reactor system to provide multi-zone substrate temperature control. The method includes, with a first pyrometer, sensing a temperature of a first zone of a substrate supported in the reactor system, and, with a second pyrometer, sensing a temperature of a second zone of the substrate. The method further includes, with a controller, comparing the temperatures of the first and second zones to setpoint temperatures for the first and second zones and, in response, generating control signals to control heating of the substrate. The method also includes controlling, based on the control signals, operations of a heater assembly operating to heat the substrate.

Abstract: A substrate support and lift assembly configured to support and lift a substrate from a susceptor is disclosed. The substrate support and lift assembly can include a susceptor support and a lift pin. The susceptor support can be configured to support the susceptor thereon. The susceptor support includes a plurality of support arms each extending radially from a central portion of the susceptor support to a terminus. Each of the plurality of support arms includes an aperture extending therethrough. The lift pin can be configured to fit through the aperture of a corresponding support arm to lift a substrate on the susceptor.

Abstract: A power semiconductor device includes a substrate, a first well, a second well, a drain, a source, a first gate structure, a second gate structure and a doping region. The first well has a first conductivity and extends into the substrate from a substrate surface. The second well has a second conductivity and extends into the substrate from the substrate surface. The drain has the first conductivity and is disposed in the first well. The source has the first conductivity and is disposed in the second well. The first gate structure is disposed on the substrate surface and at least partially overlapping with the first well and second well. The second gate structure is disposed on the substrate surface and overlapping with the second well. The doping region has the first conductivity, is disposed in the second well and connects the first gate structure with the second gate structure.

Abstract: A power semiconductor device includes a substrate, a first well, a second well, a drain, a source, a first gate structure, a second gate structure and a doping region. The first well has a first conductivity and extends into the substrate from a substrate surface. The second well has a second conductivity and extends into the substrate from the substrate surface. The drain has the first conductivity and is disposed in the first well. The source has the first conductivity and is disposed in the second well. The first gate structure is disposed on the substrate surface and at least partially overlapping with the first well and second well. The second gate structure is disposed on the substrate surface and overlapping with the second well. The doping region has the first conductivity, is disposed in the second well and connects the first gate structure with the second gate structure.

Abstract: A high-voltage FinFET device having LDMOS structure and a method for manufacturing the same are provided. The method includes: providing a substrate with a fin structure to define a first and a second type well regions; forming a trench in the first-type well region to separate the fin structure into a first part and a second part; forming a STI structure in the trench; forming a first and a second polycrystalline silicon gate stack structures at the fin structure; forming discontinuous openings on the exposed fin structure and growing an epitaxial material layer in the openings; doping the epitaxial material layer to form a drain and a source doped layers in the first and second parts respectively; and performing a RMG process to replace the first and second polycrystalline silicon gate stack structures with a first and second metal gate stack structures respectively.

Abstract: A semiconductor structure and a manufacturing method for the same are disclosed. The semiconductor structure includes a first gate structure, a second gate structure and a second dielectric spacer. Each of the first gate structure and the second gate structure adjacent to each other includes a first dielectric spacer. The second dielectric spacer is on one of opposing sidewalls of the first gate structure and without being disposed on the dielectric spacer of the second gate structure.

Abstract: A semiconductor structure and a manufacturing method for the same are disclosed. The semiconductor structure includes a first gate structure, a second gate structure and a second dielectric spacer. Each of the first gate structure and the second gate structure adjacent to each other includes a first dielectric spacer. The second dielectric spacer is on one of opposing sidewalls of the first gate structure and without being disposed on the dielectric spacer of the second gate structure.

Abstract: A high-voltage FinFET device having LDMOS structure and a method for manufacturing the same are provided. The method includes: providing a substrate with a fin structure to define a first and a second type well regions; forming a trench in the first-type well region to separate the fin structure into a first part and a second part; forming a STI structure in the trench; forming a first and a second polycrystalline silicon gate stack structures at the fin structure; forming discontinuous openings on the exposed fin structure and growing an epitaxial material layer in the openings; doping the epitaxial material layer to form a drain and a source doped layers in the first and second parts respectively; and performing a RMG process to replace the first and second polycrystalline silicon gate stack structures with a first and second metal gate stack structures respectively.