Patents by Inventor Han Yu

Han Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11348221
    Abstract: A wafer testing method adapted to test a thin wafer. The thin wafer is combined with a vacuum-release substrate to form a wafer-assembly, and the wafer-assembly is placed in a wafer cassette. The vacuum-release substrate is attached to a front surface of the wafer with an attaching force which is sensitive to air pressure. The method includes the following steps. First, taking out the wafer-assembly from the wafer cassette, then transferring the wafer-assembly to a warpage-detection-device and placing the wafer-assembly on a first stage of the warpage-detection-device. Then, detecting warpage of the wafer. If the warpage of the wafer is less than a warpage threshold, the wafer-assembly is taken out from the first stage, and the wafer-assembly is turned over to place the wafer-assembly on a second stage. Then, applying negative pressure to the vacuum-release substrate to eliminate the attaching force. Then, removing the vacuum-release substrate.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: May 31, 2022
    Assignee: MPI CORPORATION
    Inventors: Chien-Yu Chen, Han-Yu Chuang, Po-Han Peng
  • Patent number: 11342047
    Abstract: Methods and systems are provided for determining a variant of interest by analyzing sizes and sequences of cfDNA fragments obtained from a test sample. The methods and systems provided herein implement processes that synergistically combine size and sequence information, thereby improving specificity and sensitivity of assays over conventional methods.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: May 24, 2022
    Assignee: Illumina, Inc.
    Inventors: Tingting Jiang, Chen Zhao, Han-Yu Chuang
  • Publication number: 20220158160
    Abstract: Improving the performance of cathodes by using surface coatings has proven to be an effective method for improving the stability of Li-ion batteries (LIBs), while a high-quality film satisfying all requirements of electrochemical inertia, chemical stability, and lithium ion conductivity has not been found. Disclosed herein is a composite film composed of A2O3 and AlF3 layers was coated on the surface of Li1.2Mn0.54Co0.13Ni0.13O2 (Li-rich NMC) based electrodes by atomic layer deposition (ALD). By varying the ratio of Al2O3 and AlF3, an optimal coating was achieved. The electrochemical characterization results indicated that the coating with 1 cycle of AlF3 ALD on 5 cycles of Al2O3 ALD (1AlF3—5Al2O3) significantly improved the cycling stability and alleviated the voltage attenuation problem of Li-rich NMC based electrodes by suppressing side reactions between the electrolyte and electrode, as well as inhibiting the transformation of layered Li2MnO3 into a spinel-like phase.
    Type: Application
    Filed: May 11, 2020
    Publication date: May 19, 2022
    Inventors: Xinhua LIANG, Han YU
  • Publication number: 20220131006
    Abstract: In an embodiment, a device includes a first fin extending from a substrate. The device also includes a first gate stack over and along sidewalls of the first fin. The device also includes a first gate spacer disposed along a sidewall of the first gate stack. The device also includes and a first source/drain region in the first fin and adjacent the first gate spacer, the first source/drain region including a first epitaxial layer on the first fin, the first epitaxial layer having a first dopant concentration of boron. The device also includes and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having a second dopant concentration of boron, the second dopant concentration being greater than the first dopant concentration.
    Type: Application
    Filed: March 29, 2021
    Publication date: April 28, 2022
    Inventors: Hung-Tai Chang, Han-Yu Tang, Ming-Hua Yu, Yee-Chia Yeo
  • Publication number: 20220130693
    Abstract: The present disclosure provides a semiconductor fabrication apparatus. The semiconductor apparatus includes a processing chamber for etching; a substrate stage integrated in the processing chamber and being configured to secure a semiconductor wafer; a reflective mirror configured inside the processing chamber to reflect thermal energy from the heating mechanism toward the semiconductor wafer; and a heating mechanism embedded in the process chamber and is operable to perform a baking process to remove a by-product generated during the etching. The heating mechanism is integrated between the reflective mirror and a gas distribution plate of the processing chamber.
    Type: Application
    Filed: January 10, 2022
    Publication date: April 28, 2022
    Inventors: Han-Yu Lin, Yi-Ruei Jhan, Fang-Wei Lee, Li-Te Lin, Pinyen Lin, Tze-Chung Lin
  • Publication number: 20220124933
    Abstract: A server chassis includes a housing provided with a receiving cavity and an opening. A number of trays is arranged in the receiving cavity in a stacked manner. Two sides of each tray are slidably coupled to the housing. Each of the trays is configured to slide out or retract into the receiving cavity through the opening. Each of the trays is used for carrying hard disks in multiple arrays. A difference between a height of the housing and a total height of the trays is less than a height of one tray.
    Type: Application
    Filed: December 14, 2020
    Publication date: April 21, 2022
    Inventors: HAN-YU LI, WEN-HU LU, CHEN XING, SHU-YING CEN
  • Patent number: 11287253
    Abstract: The present disclosure relates to a device and a method for measuring a thickness of an ultrathin film on a solid substrate. The thickness of the target ultrathin film is measured from the intensity of the fluorescence converted by the substrate and leaking and tunneling through the target ultrathin film at low detection angle. The fluorescence generated from the substrate has sufficient and stable high intensity, and therefore can provide fluorescence signal strong enough to make the measurement performed rapidly and precisely. The detection angle is small, and therefore the noise ratio is low, and efficiency of thickness measurement according to the method disclosed herein is high. The thickness measurement method can be applied into In-line product measurement without using standard sample, and therefore the thickness of the product can be measured rapidly and efficiently.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: March 29, 2022
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chun-Ting Liu, Han-Yu Chang, Bo-Ching He, Guo-Dung Chen, Wen-Li Wu, Wei-En Fu
  • Patent number: 11291135
    Abstract: A chassis includes a receiving member, a bracket, and a sliding assembly. The bracket is configured to be mounted in a cabinet. The sliding assembly is configured to slidably mount the receiving member on the bracket.
    Type: Grant
    Filed: November 18, 2020
    Date of Patent: March 29, 2022
    Assignee: HONGFUJIN PRECISION ELECTRONICS(TIANJIN)CO., LTD.
    Inventors: Han-Yu Li, Xiang-Hui Zeng, Fan-Yin Meng
  • Patent number: 11278900
    Abstract: Microperturbation fluidic assembly systems and methods are provided for the fabrication of emissive panels. The method provides an emissive substrate with a top surface patterned to form an array of wells. A liquid suspension is formed over the emissive substrate top surface, comprising a first liquid and emissive elements. Using an array of micropores, a perturbation medium, which optionally includes emissive elements, is injected into the liquid suspension. The perturbation medium may be the first liquid, a second liquid, or a gas. A laminar flow is created in the liquid suspension along the top surface of the emissive substrate in response to the perturbation medium, and emissive elements are captured in the wells. The ejection of the perturbation medium can also be used to control the thickness of the liquid suspension overlying the top surface of the emissive substrate.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: March 22, 2022
    Assignee: eLux, Inc.
    Inventors: Kenji Sasaki, Shu-han Yu, Paul J. Schuele
  • Publication number: 20220087077
    Abstract: A power converter is provided. The power converter includes a housing, a heat dissipation module, and a first circuit board. The housing forms a receiving space, wherein the housing includes a first housing port and a second housing port. The heat dissipation module is detachably connected to the housing, and disposed in the receiving space. The heat dissipation module includes an inner path that communicates the first housing port with the second housing port. Working fluid enters the inner path via the first housing port. The working fluid leaves the inner path via the second housing port. The first circuit board includes a first circuit board body and a first heat source, wherein the first heat source is disposed on the first circuit board body, and the first heat source is thermally connected to the inner path of the heat dissipation module.
    Type: Application
    Filed: April 1, 2021
    Publication date: March 17, 2022
    Inventors: Sheng-Nan TSAI, Ying-Chung CHUANG, Chia-Jung LIU, Yi-Wei CHEN, Han-Yu TAI, Shao-Hsiang LO
  • Patent number: 11266032
    Abstract: An outer case includes an upper case, a lower case, and a plurality of guiding structures. The lower case includes a bottom wall defining a plurality of through holes. The guiding structures are arranged on the bottom wall. Each of the guiding structures includes a first guiding plate and a second guiding plate, the first guiding plate includes a first connecting part and a first blocking part connected with the first connecting part, the second guiding plate includes a second connecting part and a second blocking part connected with the second connecting part, the first connecting part and the second connecting part face each other. The first blocking part is suspended on the bottom wall through the first connecting part, the second blocking part is suspended on the bottom wall through the second connecting part, the first blocking part and the second blocking part are staggered.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: March 1, 2022
    Assignee: HONGFUJIN PRECISION ELECTRONICS (TIANJIN) CO., LTD.
    Inventors: Ya-Ni Zhang, Ming-Hua Duan, Han-Yu Li
  • Publication number: 20220045342
    Abstract: A fuel cell system capable of improving the chemical durability of a membrane electrode assembly by compensating for the amount of an antioxidant lost within the electrolyte membrane or electrode of the fuel cell stack in such a manner that the antioxidant is provided from an antioxidant supply device, provided in a fuel processing system and/or an air processing system, to a fuel cell stack, in preparation for a case where the antioxidant within the electrolyte membrane or electrode is lost due to the dissolution or migration characteristic of the antioxidant.
    Type: Application
    Filed: December 9, 2020
    Publication date: February 10, 2022
    Inventors: Jung Han Yu, Hyeon Seok Ban, Bo Ki Hong, Hyun Yoo Kim
  • Publication number: 20220045194
    Abstract: A semiconductor device structure is provided. The semiconductor device includes a first nanowire structure over a second nanowire structure, a gate stack wrapping around the first nanowire structure and the second nanowire structure, a source/drain feature adjoining the first nanowire structure and the second nanowire structure, a gate spacer layer over the first nanowire structure and between the gate stack and the source/drain feature, and an inner spacer layer between the first nanowire structure and the second nanowire structure and between the gate stack and the source/drain feature. The gate spacer layer has a first carbon concentration, the inner spacer has a second carbon concentration, and the second carbon concentration is lower than the first carbon concentration.
    Type: Application
    Filed: October 18, 2021
    Publication date: February 10, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Han-Yu LIN, Chansyun David YANG, Fang-Wei LEE, Tze-Chung LIN, Li-Te LIN, Pinyen LIN
  • Patent number: 11234341
    Abstract: A dummy chassis includes a first frame bar, a second frame bar and a connection member. The first frame bar has a first long side and a first engaging portion. The second frame bar has a second long side and a second engaging portion. The connection member has two end portions which are located oppositely. The first end portion has a third engaging portion. The second end portion has a fourth engaging portion. A width of the connection member is less than a length of the first frame bar and a length of the second frame bar.
    Type: Grant
    Filed: December 25, 2019
    Date of Patent: January 25, 2022
    Assignee: CHENBRO MICOM CO., LTD.
    Inventors: Cheng-Han Yu, Ming-Huei Hsiao, Wei-Cheng Ma
  • Publication number: 20220020644
    Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include a first channel layer and a sacrificial layer. The method can further include forming a first recess structure in a first portion of the fin structure, forming a second recess structure in the sacrificial layer of a second portion of the fin structure, forming a dielectric layer in the first and second recess structures, and performing an oxygen-free cyclic etching process to etch the dielectric layer to expose the channel layer of the second portion of the fin structure.
    Type: Application
    Filed: January 7, 2021
    Publication date: January 20, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Han-Yu LIN, Jhih-Rong Huang, Yen-Tien Tung, Tzer-Min Shen, Fu-Ting Yen, Gary Chan, Keng-Chu Lin, Li-Te Lin, Pinyen Lin
  • Publication number: 20220020595
    Abstract: A technique for semiconductor manufacturing is provided. The technique includes the operations as follows. A semiconductor structure having a first material and a second material is revived. The first material has a first incubation time to a first etching chemistry. The second material has a second incubation time to the first etching chemistry. The first incubation time is shorter than the second incubation time. A first main etch to the semiconductor structure for a first duration by the first etching chemistry is performed. The first duration is greater than the first incubation time and shorter than the second incubation time.
    Type: Application
    Filed: January 20, 2021
    Publication date: January 20, 2022
    Inventors: HAN-YU LIN, LI-TE LIN, TZE-CHUNG LIN, FANG-WEI LEE, YI-LUN CHEN, JUNG-HAO CHANG, YI-CHEN LO, FO-JU LIN, KENICHI SANO, PINYEN LIN
  • Publication number: 20220015257
    Abstract: A chassis includes a receiving member, a bracket, and a sliding assembly. The bracket is configured to be mounted in a cabinet. The sliding assembly is configured to slidably mount the receiving member on the bracket.
    Type: Application
    Filed: November 18, 2020
    Publication date: January 13, 2022
    Inventors: HAN-YU LI, XIANG-HUI ZENG, FAN-YIN MENG
  • Patent number: 11222794
    Abstract: The present disclosure provides a semiconductor fabrication apparatus. The semiconductor apparatus includes a processing chamber for etching; a substrate stage integrated in the processing chamber and being configured to secure a semiconductor wafer; a reflective mirror configured inside the processing chamber to reflect thermal energy from the heating mechanism toward the semiconductor wafer; and a heating mechanism embedded in the process chamber and is operable to perform a baking process to remove a by-product generated during the etching. The heating mechanism is integrated between the reflective mirror and a gas distribution plate of the processing chamber.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: January 11, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Han-Yu Lin, Yi-Ruei Jhan, Fang-Wei Lee, Li-Te Lin, Pinyen Lin, Tze-Chung Lin
  • Publication number: 20210405713
    Abstract: An electromagnetic leakage prevention device includes a bottom surface, first side walls, second side walls, a first connecting portion, and a second connecting portion. The first side walls are coupled to a side of the bottom surface. The second side walls are coupled to a side of the bottom surface opposite the first side walls. The first connecting portion is coupled to ends of the first side walls away from the bottom surface. The second connecting portion is coupled to ends of the second side walls away from the bottom surface. A distance between the first side walls and the second side walls increases along a direction away from the bottom surface.
    Type: Application
    Filed: October 28, 2020
    Publication date: December 30, 2021
    Inventors: YA-NI ZHANG, HAN-YU LI, CHENG-HE LI, WEN-HU LU
  • Publication number: 20210405942
    Abstract: The present disclosure provides a network connection configuration method, a network connection configuration apparatus, an image forming apparatus, and a storage medium.
    Type: Application
    Filed: September 3, 2021
    Publication date: December 30, 2021
    Inventors: Lina MENG, Yinggui CHEN, Han YU, Xiang CHEN