Patents by Inventor Han Yu

Han Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHOD FOR SEMICONDUCTOR DEVICE STRUCTURE
    Publication number: 20220336635
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming first semiconductor layers and second semiconductor layers on a substrate, and the first semiconductor layers and the second semiconductor layers are alternately stacked. The method includes forming a dummy gate structure over the first semiconductor layers and the second semiconductor layers, and removing a portion of the first semiconductor layers and second semiconductor layers to form a S/D trench. The method also includes removing the second semiconductor layers to form a recess connected to the S/D trench. The method includes forming a dummy dielectric layer in the recess after the dummy gate structure is formed, and the dummy dielectric layer is exposed by the S/D trench. The method includes removing a portion of the dummy dielectric layer to form a cavity and forming an inner spacer layer in the cavity.
    Type: Application
    Filed: June 30, 2022
    Publication date: October 20, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tze-Chung LIN, Han-Yu LIN, Li-Te LIN, Pinyen LIN
  • TECHNIQUE FOR SEMICONDUCTOR MANUFACTURING
    Publication number: 20220319861
    Abstract: A technique for semiconductor manufacturing is provided. The technique includes the operations as follows. A semiconductor structure having a first material is received. A plurality of first main etches are performed to the semiconductor structure for a plurality of first durations under the first etching chemistry. A plurality of pumping operations are performed for a plurality of pumping durations, each of the pumping operations being prior to each of the first main etches. Each of the first durations is in a range of from about 1 second to about 2.5 seconds.
    Type: Application
    Filed: June 24, 2022
    Publication date: October 6, 2022
    Inventors: HAN-YU LIN, LI-TE LIN, TZE-CHUNG LIN, FANG-WEI LEE, YI-LUN CHEN, JUNG-HAO CHANG, YI-CHEN LO, FO-JU LIN, KENICHI SANO, PINYEN LIN
  • Contact Structures in Semiconductor Devices
    Publication number: 20220310800
    Abstract: The present disclosure describes a semiconductor device and a method for forming the semiconductor device. The method includes forming a fin structure on a substrate, forming a gate structure on the fin structure, and forming a source/drain (S/D) region on the fin structure not covered by the gate structure. The method further includes forming a contact structure on the S/D region. Forming the contact structure includes forming a transition metal chalcogenide (TMC) layer on the S/D region, and forming a contact plug on the TMC layer.
    Type: Application
    Filed: November 23, 2021
    Publication date: September 29, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mrunal Abhijith Khaderbad, Wei-Yen WOON, Cheng-Ming LIN, Han-Yu LIN, Szu-Hua CHEN
  • Universal short adapters with variable length non-random unique molecular identifiers
    Patent number: 11447818
    Abstract: The disclosed embodiments concern methods, systems and computer program products for determining sequences of interest using unique molecular indexes (UMIs) that are uniquely associable with individual polynucleotide fragments, including sequences with low allele frequencies or long sequence length. In some implementations, the UMIs include variable-length nonrandom UMIs (vNRUMIs). Methods and systems for making and using sequencing adapters comprising vNRUMIs are also provided.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: September 20, 2022
    Assignee: Illumina, Inc.
    Inventors: Chen Zhao, Kevin Wu, Han-Yu Chuang, Jennifer Lococo, Alex So, Dwight Baker, Tatjana Singer
  • GRAPHENE LAYER FOR LOW RESISTANCE CONTACTS AND DAMASCENE INTERCONNECTS
    Publication number: 20220285221
    Abstract: The present disclosure provides low resistance contacts and damascene interconnects with one or more graphene layers in fin structures of FETs. An example semiconductor device can include a substrate with a fin structure that includes an epitaxial region. The semiconductor device can also include an etch stop layer on the epitaxial region, and an interlayer dielectric layer on the etch stop layer. The semiconductor device can further include a metal contact, above the epitaxial region, formed through the etch stop layer and the interlayer dielectric layer, and a graphene film at interfaces between the metal contact and each of the epitaxial region, the etch stop layer, and the interlayer dielectric layer.
    Type: Application
    Filed: December 14, 2021
    Publication date: September 8, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mrunal Abhijith Khaderbad, Wei-Yen Woon, Cheng-Ming Lin, Han-Yu Lin, Szu-Hua Chen, Jhih-Rong Huang, Tzer-Min Shen
  • Semiconductor device structure and method for forming the same
    Patent number: 11417751
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a plurality of first semiconductor layers and a plurality of second semiconductor layers on a substrate, and the first semiconductor layers and the second semiconductor layers are alternately stacked. The method also includes forming a dummy gate structure over the first semiconductor layers and the second semiconductor layers. The method further includes removing a portion of the first semiconductor layers and second semiconductor layers to form a trench, and removing the second semiconductor layers to form a recess between two adjacent first semiconductor layers. The method includes forming a dummy dielectric layer in the recess, and removing a portion of the dummy dielectric layer to form a cavity. The method also includes forming an inner spacer layer in the cavity.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: August 16, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tze-Chung Lin, Han-Yu Lin, Li-Te Lin, Pinyen Lin
  • Electronic device for recognizing fingerprint using display
    Patent number: 11410454
    Abstract: According to an embodiment disclosed herein, an electronic device may include a housing, a display panel including a plurality of pixels housed in the housing, a flexible printed circuit board electrically connected to the display panel, a fingerprint sensor disposed under at least a portion of the display panel and on the flexible printed circuit board, a display driver integrated circuit (IC) and a processor electrically connected to the fingerprint sensor and the display driver IC.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: August 9, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong Kon Bae, Yo Han Lee, Yun Pyo Hong, Dong Hwy Kim, Han Yu Ool Kim, Dong Kyoon Han, Kwang Tai Kim
  • USING CELL-FREE DNA FRAGMENT SIZE TO DETECT TUMOR-ASSOCIATED VARIANT
    Publication number: 20220246234
    Abstract: Methods and systems are provided for determining a variant of interest by analyzing sizes and sequences of cfDNA fragments obtained from a test sample. The methods and systems provided herein implement processes that synergistically combine size and sequence information, thereby improving specificity and sensitivity of assays over conventional methods.
    Type: Application
    Filed: April 20, 2022
    Publication date: August 4, 2022
    Inventors: Tingting Jiang, Chen Zhao, Han-Yu Chuang
  • SEMICONDUCTOR DEVICE AND METHODS OF FORMING
    Publication number: 20220246611
    Abstract: An embodiment includes a first fin extending from a substrate. The device also includes a first gate stack over and along sidewalls of the first fin. The device also includes a first gate spacer disposed along a sidewall of the first gate stack. The device also includes a first epitaxial source/drain region in the first fin and adjacent the first gate spacer, an outer surface of the epitaxial first source/drain region having more than eight facets in a first plane, the first plane being orthogonal to a top surface of the substrate.
    Type: Application
    Filed: January 29, 2021
    Publication date: August 4, 2022
    Inventors: Han-Yu Tang, Hung-Tai Chang, Ming-Hua Yu, Yee-Chia Yeo
  • Server equipment and its latch mechanism
    Patent number: 11406031
    Abstract: A latch mechanism includes a bracket, a sliding element slidably located on the bracket, a latch portion fixedly connected to the sliding element, an elastic element connected to the bracket and the sliding element, and a trigger element including an elongated frame, a through hole and a pressed portion. The elongated frame is slidably located on the bracket, the through hole is formed on one surface of the elongated frame, and the pressed portion is disposed on the one surface of the elongated frame, and directly pressed by the latch portion. When the trigger element is pushed until the through hole is moved to the latch portion, the first elastic element moves the latch portion to extend into the through hole.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: August 2, 2022
    Assignee: CHENBRO MICOM CO., LTD.
    Inventor: Cheng-Han Yu
  • Electromagnetic leakage prevention device and component fixing member
    Patent number: 11402881
    Abstract: An electromagnetic leakage prevention device includes a bottom surface, first side walls, second side walls, a first connecting portion, and a second connecting portion. The first side walls are coupled to a side of the bottom surface. The second side walls are coupled to a side of the bottom surface opposite the first side walls. The first connecting portion is coupled to ends of the first side walls away from the bottom surface. The second connecting portion is coupled to ends of the second side walls away from the bottom surface. A distance between the first side walls and the second side walls increases along a direction away from the bottom surface.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: August 2, 2022
    Assignee: Fulian Precision Electronics (Tianjin) Co., LTD.
    Inventors: Ya-Ni Zhang, Han-Yu Li, Cheng-He Li, Wen-Hu Lu
  • FIXING STRUCTURE FOR HARD DISK AND SERVER CHASSIS HAVING THE SAME
    Publication number: 20220236775
    Abstract: A fixing structure for a hard disk is provided, which includes a main body, a rotation member, and at least one latching post. The main body includes two first sidewalls and a second sidewall connecting therebetween. The main body defines a groove for receiving the hard disk. At least one first sidewall defines a limiting slot. The rotation member includes two rotation arms, at least one rotation arm defines a latching slot. The rotation arms are rotatably connected to the two first sidewalls, to cause the fixing structure to be capable of switching between a first state and a second state. Each latching post is movably disposed in one limiting slot and one latching slot. When the fixing structure is switched between the first direction and the second state, the main body can move along a first direction or a second direction.
    Type: Application
    Filed: October 29, 2021
    Publication date: July 28, 2022
    Inventors: HAN-YU LI, WEN-HU LU, CHEN XING, SHU-YING CEN
  • LIGHT-EMITTING FILM, LIGHT-EMITTING FILM ARRAY, MICRO LIGHT EMITTING DIODE ARRAY, AND MANUFACTURING METHOD THEREOF
    Publication number: 20220209074
    Abstract: Embodiments of the present invention provide a light-emitting film, a light-emitting film array, a micro-light emitting diode (LED) array, and their manufacturing methods. In one embodiment, epitaxial layers are formed on a substrate, and a conversion film is formed on a corresponding epitaxial layer. Pixels can be defined through lithography with a very small pixel size. A mass transfer is unnecessary for this method. The produced light-emitting films and the conversion films are homogeneous films and are insoluble in water, and the manufacturing steps can be simplified due to the waterproofing function of the films.
    Type: Application
    Filed: March 30, 2021
    Publication date: June 30, 2022
    Inventors: Ching-Fuh Lin, Jung-Kuan Huang, Teng-Yi Huang, Yi-Shan Lin, Han-Yu Tsai
  • Technique for semiconductor manufacturing
    Patent number: 11373878
    Abstract: A technique for semiconductor manufacturing is provided. The technique includes the operations as follows. A semiconductor structure having a first material and a second material is revived. The first material has a first incubation time to a first etching chemistry. The second material has a second incubation time to the first etching chemistry. The first incubation time is shorter than the second incubation time. A first main etch to the semiconductor structure for a first duration by the first etching chemistry is performed. The first duration is greater than the first incubation time and shorter than the second incubation time.
    Type: Grant
    Filed: January 20, 2021
    Date of Patent: June 28, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Han-Yu Lin, Li-Te Lin, Tze-Chung Lin, Fang-Wei Lee, Yi-Lun Chen, Jung-Hao Chang, Yi-Chen Lo, Fo-Ju Lin, Kenichi Sano, Pinyen Lin
  • Testing device with power protection and its testing platform
    Patent number: 11360116
    Abstract: A testing device with power protection includes a power interface and a testing platform. The testing platform includes a casing, a fixed frame and a sliding frame. The power interface is disposed at one surface of the casing. The fixed frame covers the power interface. One side of the fixed frame formed with an entrance that exposes the power interface outwards from the fixed frame. The sliding frame includes a rack body slidably that is located on the casing, and a shielding door that is rotatably connected to the rack body for covering the entrance of the fixed frame. When the rack body is slid towards the power interface so as to rotate the shielding door away from the entrance by the fixed frame, the power interface is exposed outwards from the fixed frame through the entrance.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: June 14, 2022
    Assignee: CHENBRO MICOM CO., LTD.
    Inventor: Cheng-Han Yu
  • LOWER LIMB REHABILITATION SYSTEM BASED ON AUGMENTED REALITY AND BRAIN COMPUTER INTERFACE
    Publication number: 20220175275
    Abstract: A lower limb rehabilitation system based on augmented reality and a brain computer interface includes a display, a plurality of motion sensors, a brain wave monitor, and an analysis platform. The display is configured to receive and play a virtual scene video to guide a user to perform gait rehabilitation training. The plurality of motion sensors is configured to sense gait data. The brain wave monitor is configured to record an electroencephalogram signal by detecting an electric current change in a brain wave of the user. The analysis platform is configured to compare the gait data with the virtual scene video to determine the accuracy of footsteps of the user and provide feedback. The analysis platform inputs the electroencephalogram signal to a machine learning model to quantify the electroencephalogram signal into an index value representing a lower limb motor function of the user.
    Type: Application
    Filed: November 29, 2021
    Publication date: June 9, 2022
    Inventors: CHIA-HSIN CHEN, LI-WEI KO, YI-JEN CHEN, WEI-CHIAO CHANG, BO-YU TSAI, KUEN-HAN YU
  • CATALYST COMPLEX FOR FUEL CELLS AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20220181642
    Abstract: Disclosed are a catalyst complex which may suppress cell voltage reversal in a fuel cell and a method for manufacturing the same. The catalyst complex includes a support, a first catalytic active material supported on the support and comprising a platinum component including one or more selected from the group consisting of platinum and a platinum alloy, and a second catalytic active material supported on the support and comprising one or more selected from a noble metal other than platinum and an oxide thereof, and the support includes functional groups including oxygen.
    Type: Application
    Filed: August 10, 2021
    Publication date: June 9, 2022
    Inventors: Dae Yong Son, Jung Han Yu, Byoung Su Kim, Hyun Joo Lee, Hee Eun Kim
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20220173224
    Abstract: A method includes forming a fin structure including a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked over a substrate. A dummy gate structure is formed across the fin structure. The exposed second portions of the fin structure are removed. A selective etching process is performed, using a gas mixture including a hydrogen-containing gas and a fluorine-containing gas, to laterally recess the first semiconductor layers. Inner spacers are formed on opposite end surfaces of the laterally recessed first semiconductor layers. Source/drain epitaxial structures are formed on opposite end surfaces of the second semiconductor layers. The dummy gate structure is removed to expose the first portion of the fin structure. The laterally recessed first semiconductor layers are removed. A gate structure is formed to surround each of the second semiconductor layers.
    Type: Application
    Filed: January 19, 2021
    Publication date: June 2, 2022
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC Nanjing Company Limited
    Inventors: Han-Yu LIN, Fang-Wei LEE, Kai-Tak LAM, Raghunath PUTIKAM, Tzer-Min SHEN, Li-Te LIN, Pinyen LIN, Cheng-Tzu YANG, Tzu-Li LEE, Tze-Chung LIN
  • Computer and support member
    Patent number: 11347274
    Abstract: A computer includes a chassis, a circuit board installed in the chassis, and a support member. The support member includes a support portion, a first clamping portion, and a second clamping portion. The first clamping portion and the second clamping portion are respectively located at two ends of the support portion. The first clamping portion is configured to clamp the circuit board. The second clamping portion is configured to clamp the chassis.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: May 31, 2022
    Assignee: Fulian Precision Electronics (Tianjin) Co., LTD.
    Inventors: Ming-Pei Zhang, Ya-Ni Zhang, Han-Yu Li
  • LED luminaire housing
    Patent number: D959721
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: August 2, 2022
    Inventor: Chung Han Yu