Abstract: Reduction of program disturb degradation in a flash memory cell array is facilitated by selectively switching wordline voltage levels in a sequence that reduces the likelihood of trapping electrons in memory cell channels. During a program verify operation for a memory cell in a memory cell string, a flash memory system switches wordline voltage levels from high-to-low for interface wordlines, prior to switching wordline voltages from high-to-low for other wordlines in a memory cell string. Selectively switching wordlines in a sequence in the memory cell string enables electrons to migrate to ground or to a source voltage through upper and lower select gates.

Abstract: Embodiments of the present invention provide a reconfigurable optical add/drop multiplexer, including: an input component, an output component, a beamsplitter, a first switch array, a wavelength dispersion system, a redirection system, and a second switch array. The input component includes M+P input ports, the output component includes N output ports, the beamsplitter is configured to: receive M input beams from M input ports, and split each of the M input beams into at least N parts, to obtain at least M×N beams; the first switch array includes at least P switch units; and the second switch array includes N rows of switch units. The first switch array, the beamsplitter, the wavelength dispersion system, the redirection system, and the second switch array are arranged so that P optical add beams and sub-beams of M×N beams in the at least M×N beams can be routed to the N output ports.

Abstract: A wavelength switching apparatus includes M input components, a first optical component, a first switch array, a second switch array, a second optical component, and K output components. The M input components include at least one local input component having N input ports, and a light beam input by the local input component can be converged, under an action of the first optical component, on a row of switch units that are in the first switch array and that are corresponding to the local input component. In this way, this is equivalent to further connecting an N*1-dimensional WSS to an input end of an M*K-dimensional WSS, so that the wavelength switching apparatus can integrate a wavelength adding function based on the M*K-dimensional WSS.

Abstract: A frequency offset processing method, apparatus, and a storage medium, where the method includes: determining a frequency offset of a preset channel in a wavelength selective switch (WSS); determining a correspondence between a frequency offset and a wavelength or a correspondence between a frequency offset and a pixel position based on the frequency offset of the preset channel; and determining a frequency offset of a traffic channel according to the determined correspondence.

Abstract: A liquid crystal on silicon, a wavelength selective switch, an alignment direction obtaining method, and a method for manufacturing a liquid crystal on silicon. The liquid crystal on silicon has a first pixel area, and a first liquid crystal located in the first pixel area. The first liquid crystal is deflected in a plane perpendicular to a first panel, and is deflected towards a first direction in a plane parallel to the first panel. An alignment direction of the first partial alignment film located in the first pixel area is deflected towards a second direction relative to a polarization direction of an incident beam, and the second direction is opposite to the first direction to reduce a loss of a deflected beam.

Abstract: Memories having a controller configured to perform methods during programming operations including apply a first voltage level to a data line selectively connected to a selected memory cell selected, apply a lower second voltage level to a select gate connected between the data line and the memory cell, decrease the voltage level applied to the data line from the first voltage level to a third voltage level while continuing to apply the second voltage level to the select gate, increase the voltage level applied to the select gate from the second voltage level to a fourth voltage level after the voltage level of the data line settles to the third voltage level, and apply a programming voltage to the memory cell after increasing the voltage level applied to the select gate to the fourth voltage level.

Abstract: The invention provides a method for separating a mammal early follicle to obtain a single oocyte and a single granulocyte thereof. The method is capable of separating a mammal early follicle to obtain an active single oocyte and a corresponding granulocyte thereof. The invention further provides a kit for obtaining a single oocyte and a single granulocyte thereof from a mammal early follicle.

Abstract: A transfer impedance calibration device for transducers based on spatial frequency domain smoothing technology is provided. The calibration device comprises a signal transmitter, a power amplifier, a transducer pair, a measurement amplifier, a signal collector, a measurement processor and a current sampler. The device extracts acoustic channel information through the sound filed spatial information or measurement method to design a spatial domain smoothing filter, and then comprehensively processes the transmitted current signal and the received signal through the spatial frequency domain smoothing technology to obtain the transfer impedance of the transducer pair.

Abstract: Methods of operating a memory include activating a respective memory cell of each string of series-connected memory cells of a plurality of strings of series-connected memory cells, selectively activating a target memory cell of a selected string of series-connected memory cells of the plurality of strings of series-connected memory cells depending upon its data state, and deactivating a respective memory cell of each string of series-connected memory cells of a first subset of the plurality of strings of series-connected memory cells.

Abstract: A technique for read or program verify (PV) operations for non-volatile memory is described. In one example, at the end of a program verify operation (e.g., during a program verify recovery phase), a number of wordlines near a selected wordline are ramped down one at a time. Ramping down wordlines near the selected wordline one at a time can significantly reduce the trapped charge in the channel, enabling lower program disturb rates and improved threshold voltage distributions. In one example, the same technique of ramping down wordlines near the selected wordline can be applied to a read operation.

Abstract: A method of free-field broadband calibration of hydrophone sensitivity based on pink noise, relating to the field of free-field underwater acoustic measurement, and is mainly used for broadband measurements of hydrophone sensitivity in free-field. The method of the present disclosure is to transmit a broadband pink noise signal by controlling the signal source, and to perform the synchronous processing and FFT to the transmitted current signal and the received voltage signal, such as interception and zero padding, and finally obtain the transfer function in the frequency domain; by analyzing the direct wave and the reflected wave in the water tank, the transfer function is averaged by a rectangular window to eliminate the influence of the reverberation of the reflected wave in the water tank, so as to obtain the broadband transfer function of the free-field between the transmitting transducer and the hydrophone.

Abstract: Reduction of program disturb degradation in a flash memory cell array is facilitated by selectively switching wordline voltage levels in a sequence that reduces the likelihood of trapping electrons in memory cell channels. During a program verify operation for a memory cell in a memory cell string, a flash memory system switches wordline voltage levels from high-to-low for interface wordlines, prior to switching wordline voltages from high-to-low for other wordlines in a memory cell string. Selectively switching wordlines in a sequence in the memory cell string enables electrons to migrate to ground or to a source voltage through upper and lower select gates.

Abstract: The present invention clones a gene ZmNLP5 from maize, which plays an important regulatory role in nitrogen assimilation, and the open reading frame of which has a DNA sequence shown as SEQ ID NO:1. The transcription factor protein encoded by the ZmNLP5 gene has an amino acid sequence shown as SEQ ID NO:2. The uses of the maize NLP transcription factor ZmNLP5 mentioned above in promoting expression of a nitrogen metabolic key enzyme gene ZmNIR1.1, in promoting expression of a nitrogen metabolic key enzyme gene ZmNIR1.2, in promoting expression of a nitrogen metabolic key enzyme gene ZmNR1.1, in promoting expression of a nitrogen metabolic key enzyme gene ZmNR1.2, in improving nitrogen assimilation in maize, and in promoting elongation growth of maize root in deficient nitrogen environment are further provided.

Abstract: A technique for read or program verify (PV) operations for non-volatile memory is described. In one example, at the end of a program verify operation (e.g., during a program verify recovery phase), a number of wordlines near a selected wordline are ramped down one at a time. Ramping down wordlines near the selected wordline one at a time can significantly reduce the trapped charge in the channel, enabling lower program disturb rates and improved threshold voltage distributions. In one example, the same technique of ramping down wordlines near the selected wordline can be applied to a read operation.

Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.

Abstract: Memories having a controller configured to perform methods during programming operations including applying a first voltage level to first and second data lines while applying a second, lower, voltage level to first and second select gates connected between the data lines and respective strings of memory cells; decreasing a voltage level of the first data line to a third voltage level; increasing a voltage level of the first select gate to a fourth voltage level; applying a fifth voltage level, higher than the first voltage level, to first and second access lines coupled to memory cells of the strings of memory cells; and increasing a voltage level of the first access line to a sixth voltage level.

Abstract: Methods of operating a memory include activating a respective memory cell of each string of series-connected memory cells of a plurality of strings of series-connected memory cells, selectively activating a target memory cell of a selected string of series-connected memory cells of the plurality of strings of series-connected memory cells depending upon its data state, and deactivating a respective memory cell of each string of series-connected memory cells of a first subset of the plurality of strings of series-connected memory cells.

Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.

Abstract: Embodiments of the present invention provide a reconfigurable optical add/drop multiplexer, including: an input component, an output component, a beamsplitter, a first switch array, a wavelength dispersion system, a redirection system, and a second switch array. The input component includes M+P input ports, the output component includes N output ports, the beamsplitter is configured to: receive M input beams from M input ports, and split each of the M input beams into at least N parts, to obtain at least M×N beams; the first switch array includes at least P switch units; and the second switch array includes N rows of switch units. The first switch array, the beamsplitter, the wavelength dispersion system, the redirection system, and the second switch array are arranged so that P optical add beams and sub-beams of M×N beams in the at least M×N beams can be routed to the N output ports.

Abstract: A liquid crystal on silicon, a wavelength selective switch, an alignment direction obtaining method, and a method for manufacturing a liquid crystal on silicon. The liquid crystal on silicon has a first pixel area, and a first liquid crystal located in the first pixel area. The first liquid crystal is deflected in a plane perpendicular to a first panel, and is deflected towards a first direction in a plane parallel to the first panel. An alignment direction of the first partial alignment film located in the first pixel area is deflected towards a second direction relative to a polarization direction of an incident beam, and the second direction is opposite to the first direction to reduce a loss of a deflected beam.