Abstract: Apparatus having a plurality of strings of series-connected memory cells, and methods of their operation, where each string of the plurality of strings is selectively connected to a common data line through a corresponding respective select gate. A first set of access lines are each coupled to a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells. A second set of access lines are each coupled to a respective memory cell of each string of series-connected memory cells of only a portion of the plurality of strings of series-connected memory cells.

Abstract: Reduction of program disturb degradation in a flash memory cell array is facilitated by selectively switching wordline voltage levels in a sequence that reduces the likelihood of trapping electrons in memory cell channels. During a program verify operation for a memory cell in a memory cell string, a flash memory system switches wordline voltage levels from high-to-low for interface wordlines, prior to switching wordline voltages from high-to-low for other wordlines in a memory cell string. Selectively switching wordlines in a sequence in the memory cell string enables electrons to migrate to ground or to a source voltage through upper and lower select gates.

Abstract: Apparatus having a plurality of strings of series-connected memory cells, and methods of their operation, where each string of series-connected memory cells of the plurality of strings of series-connected memory cells may be selectively connected to a common data line through a corresponding respective select gate, a first set of access lines may each be coupled to a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells, and a second set of access lines may each be coupled to a respective memory cell of each string of series-connected memory cells of only a portion of the plurality of strings of series-connected memory cells.

Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.

Abstract: Aspects include computing devices, systems, and methods for implementing scheduling and execution of lightweight kernels as simple tasks directly by a thread without setting up a task structure. A computing device may determine whether a task pointer in a task queue is a simple task pointer for the lightweight kernel. The computing device may schedule a first simple task for the lightweight kernel for execution by the thread. The computing device may retrieve, from an entry of a simple task table, a kernel pointer for the lightweight kernel. The entry in the simple task table may be associated with the simple task pointer. The computing device may directly execute the lightweight kernel as the simple task.

Abstract: Embodiments include computing devices, apparatus, and methods implemented by the apparatus for implementing data flow management on a computing device. Embodiment methods may include initializing a buffer partition of a first memory of a first heterogeneous processing device for an output of execution of a first iteration of a first operation by the first heterogeneous processing device on which a first iteration of a second operation assigned for execution by a second heterogeneous processing device depends. Embodiment methods may include identifying a memory management operation for transmitting the output by the first heterogeneous processing device from the buffer partition as an input to the second heterogeneous processing device. Embodiment methods may include allocating a second memory for storing data for an iteration executed by a third heterogeneous processing device to minimize a number of memory management operations for the second allocated memory.

Abstract: A wavelength selective switch (WSS), including an input optical fiber collimation array, a first optical switching engine, a dispersion device, an optical path converter, a second optical switching engine, a third optical switching engine, and an output optical fiber collimation array. A first beam is input from a first port of the input optical fiber collimation array. The first optical switching engine performs angle deflection on the first beam on a first plane. The dispersion device demultiplexes, on a second plane, the angle-deflected first beam into multiple sub-wavelength beams. The second optical switching engine performs angle deflection on the multiple sub-wavelength beams that are obtained by demultiplexing. The dispersion device multiplexes, on the second plane, the angle-deflected multiple sub-wavelength beams. The third optical switching engine performs angle deflection on the multiplexed multiple sub-wavelength beams on the first plane.

Abstract: Embodiments include computing devices, systems, and methods identifying enhanced synchronization operation outcomes. A computing device may receive a first resource access request for a first resource of a computing device including a first requester identifier from a first computing element of the computing device. The computing device may also receive a second resource access request for the first resource including a second requester identifier from a second computing element of the computing device. The computing device may grant the first computing element access to the first resource based on the first resource access request, and return a response to the second computing element including the first requester identifier as a winner computing element identifier.

Abstract: Embodiments of the present invention provide a reconfigurable optical add/drop multiplexer, including: an input component, an output component, a beamsplitter, a first switch array, a wavelength dispersion system, a redirection system, and a second switch array. The input component includes M+P input ports, the output component includes N output ports, the beamsplitter is configured to: receive M input beams from M input ports, and split each of the M input beams into at least N parts, to obtain at least M×N beams; the first switch array includes at least P switch units; and the second switch array includes N rows of switch units. The first switch array, the beamsplitter, the wavelength dispersion system, the redirection system, and the second switch array are arranged so that P optical add beams and sub-beams of M×N beams in the at least M×N beams can be routed to the N output ports.

Abstract: A wavelength selective switch (WSS) includes a liquid crystal on silicon (LCOS) panel and a fiber array with multiple ports. The two outermost ports of the multiple ports are a first port and a second port. An included angle between an intersecting line of the LCOS panel and a first plane in which the incident light entering the LCOS panel and emergent light exiting the LCOS panel are located, and incident light entering the LCOS panel is (90??) degrees, where a wavelength of the incident light is same as a wavelength of the emergent light, ? is less than 15 degrees, the first port and the included angle of (90??) degrees are located on a same side of the incident light, and the second port and the included angle of (90??) degrees are separately located on two sides of the incident light.

Abstract: A wavelength selective switch (WSS), including an input optical fiber collimation array, a first optical switching engine, a dispersion device, an optical path converter, a second optical switching engine, a third optical switching engine, and an output optical fiber collimation array. A first beam is input from a first port of the input optical fiber collimation array. The first optical switching engine performs angle deflection on the first beam on a first plane. The dispersion device demultiplexes, on a second plane, the angle-deflected first beam into multiple sub-wavelength beams. The second optical switching engine performs angle deflection on the multiple sub-wavelength beams that are obtained by demultiplexing. The dispersion device multiplexes, on the second plane, the angle-deflected multiple sub-wavelength beams. The third optical switching engine performs angle deflection on the multiplexed multiple sub-wavelength beams on the first plane.

Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.

Abstract: A vertical-mode tunnel field-effect transistor (TFET) is provided with an oxide region that may be laterally positioned relative to a source region. The oxide region operates to reduce a tunneling effect in a tunnel region underlying a drain region, during an OFF-state of the TFET. The reduction in tunneling effect results in a reduction or elimination of a flow of OFF-state leakage current between the source region and the drain region. The TFET may have components made from group III-V compound materials.

Abstract: Embodiments include computing devices, apparatus, and methods implemented by the apparatus for implementing data flow management on a computing device. Embodiment methods may include initializing a buffer partition of a first memory of a first heterogeneous processing device for an output of execution of a first iteration of a first operation by the first heterogeneous processing device on which a first iteration of a second operation assigned for execution by a second heterogeneous processing device depends. Embodiment methods may include identifying a memory management operation for transmitting the output by the first heterogeneous processing device from the buffer partition as an input to the second heterogeneous processing device. Embodiment methods may include allocating a second memory for storing data for an iteration executed by a third heterogeneous processing device to minimize a number of memory management operations for the second allocated memory.

Abstract: Embodiments include computing devices, apparatus, and methods implemented by the apparatus for implementing speculative loop iteration partitioning (SLIP) for heterogeneous processing devices. A computing device may receive iteration information for a first partition of iterations of a repetitive process and select a SLIP heuristic based on available SLIP information and iteration information for the first partition. The computing device may determine a split value for the first partition using the SLIP heuristic, and partition the first partition using the split value to produce a plurality of next partitions.

Abstract: Embodiments include computing devices, apparatus, and methods implemented by the apparatus for implementing shared virtual index translation on a computing device. The computing device may receive a base virtual address for storing an output of a kernel function execution to a dedicated memory and determine whether the virtual address is in a range of virtual addresses for a privatized output buffer within the dedicated memory, which may be smaller than the dedicated memory. The computing device may calculate a first modified physical address using a physical address mapped to the base virtual address and an offset of a first processing device associated with the dedicated memory in response to determining that the base virtual address is in the range of virtual addresses. The computing device may store the output of the kernel function execution to the privatized output buffer at the first modified physical address.

Abstract: Apparatus having a plurality of strings of series-connected memory cells, and methods of their operation, where each string of the plurality of strings is selectively connected to a common data line through a corresponding respective select gate. A first set of access lines are each coupled to a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells. A second set of access lines are each coupled to a respective memory cell of each string of series-connected memory cells of only a portion of the plurality of strings of series-connected memory cells.

Abstract: Various embodiments provide methods, devices, and non-transitory processor-readable storage media enabling joint goals, such as joint power and performance goals, to be realized on a per heterogeneous processing device basis for heterogeneous parallel computing constructs. Various embodiments may enable assignments of power states for heterogeneous processing devices on a per heterogeneous processing device basis to satisfy an overall goal on the heterogeneous processing construct. Various embodiments may enable dynamic adjustment of power states for heterogeneous processing devices on a per heterogeneous processing device basis.

Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.

Abstract: A vertical-mode tunnel field-effect transistor (TFET) is provided with an oxide region that may be laterally positioned relative to a source region. The oxide region operates to reduce a tunneling effect in a tunnel region underlying a drain region, during an OFF-state of the TFET. The reduction in tunneling effect results in a reduction or elimination of a flow of OFF-state leakage current between the source region and the drain region. The TFET may have components made from group III-V compound materials.