Patents by Inventor Hanan Potash

Hanan Potash has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11093286
    Abstract: A computing device includes one or more processors and one or more memory devices. The computing device comprises a Civilware tier configured to perform one or more resource management functions in the computing device. In some embodiments, the Civilware tier includes a resource manager that is at least partially programmable to manage one or more functions in the computing device. The Civilware tier may enforce one or more rules of behavior in the computing device. In some embodiments, the computing device further includes an instructions interpretation tier. The rules enforced by the Civilware tier are independent of the specifics of the algorithms executed in the instruction interpretation tier (e.g., the Civilware tier is orthogonal to the instruction interpretation tier).
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: August 17, 2021
    Inventor: Hanan Potash
  • Patent number: 11062068
    Abstract: An electronic computer-aided design tool includes a design module and a printed electronics printer coupled to the design module. The design module determines one or more design specifications for an electronic device. The printed electronics printer produces one or more printed electronics prototypes of the electronic device based at least in part on at least on at least one of the design specifications. In some embodiments, the electronic computer-aided design tool includes a prototype testing unit that tests prototypes made by the printed electronics printer.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: July 13, 2021
    Inventor: Hanan Potash
  • Publication number: 20210103443
    Abstract: A computing device includes a plurality of bins distributed in a plurality of frames, and a plurality of mentor circuits. The bins store information for variables. Each mentor circuit may be assigned to a particular one or more of the variables. The mentor circuits perform cache management and operand addressing operations with respect to the particular variables to which the mentor circuit is assigned. A control circuit controls a main program flow.
    Type: Application
    Filed: October 19, 2020
    Publication date: April 8, 2021
    Inventor: Hanan Potash
  • Patent number: 10810010
    Abstract: A computing device includes a plurality of bins distributed in a plurality of frames, and a plurality of mentor circuits. The bins store information for variables. Each mentor circuit may be assigned to a particular one or more of the variables. The mentor circuits perform cache management and operand addressing operations with respect to the particular variables to which the mentor circuit is assigned. A control circuit controls a main program flow.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: October 20, 2020
    Inventor: Hanan Potash
  • Publication number: 20190179634
    Abstract: A computing device includes a plurality of bins distributed in a plurality of frames, and a plurality of mentor circuits. The bins store information for variables. Each mentor circuit may be assigned to a particular one or more of the variables. The mentor circuits perform cache management and operand addressing operations with respect to the particular variables to which the mentor circuit is assigned. A control circuit controls a main program flow.
    Type: Application
    Filed: November 19, 2018
    Publication date: June 13, 2019
    Inventor: Hanan Potash
  • Patent number: 10140122
    Abstract: A computer processor includes an operands-mapped namespace and/or a Variables mapped namespace. In some embodiments, a system for performing computing operations includes a processor comprising a namespace; and one or more memory devices physically or logically connected to the processor, wherein the memory devices comprise memory space. The namespace of the processor is not limited to the memory space of the one or more memory devices. In an embodiment, a method of computing includes physically or logically connecting a processor to one or more memory devices comprising memory space, and implementing, by the processor, a namespace, in which the namespace is not limited to the memory space to which the memory space is physically or logically connected.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: November 27, 2018
    Inventor: Hanan Potash
  • Publication number: 20180336303
    Abstract: An electronic computer-aided design tool includes a design module and a printed electronics printer coupled to the design module. The design module determines one or more design specifications for an electronic device. The printed electronics printer produces one or more printed electronics prototypes of the electronic device based at least in part on at least on at least one of the design specifications. In some embodiments, the electronic computer-aided design tool includes a prototype testing unit that tests prototypes made by the printed electronics printer.
    Type: Application
    Filed: May 21, 2018
    Publication date: November 22, 2018
    Inventor: Hanan Potash
  • Patent number: 10095641
    Abstract: A computing device includes a main memory; a local high speed memory; one or more functional units, one or more interconnects between the main memory and the local high speed memory, and one or more interconnects between the local high speed memory and the one or more functional units. The local high speed memory implements a frames/bins structure. The local high speed memory includes a plurality of frames, each of at least two of the frames comprising a physical memory element; and a plurality of bins distributed in the plurality of frames. Each of the bins includes a logical element. The functional units perform operations relating to Variables stored in the bins, each of the Variables including one or more words.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: October 9, 2018
    Inventor: Hanan Potash
  • Patent number: 10067878
    Abstract: A computing device includes a memory structure storing one or more Variables; and a logical mentor. The logical mentor is assigned to at least one of the one or more Variables and performs addressing operations with respect to the Variables to which it is assigned. In an embodiment, a method of computing includes storing one or more Variables in the memory of a computing device, assigning a logical mentor to the Variables; and performing, by the logical mentor, addressing operations with respect to the Variables.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: September 4, 2018
    Inventor: Hanan Potash
  • Patent number: 10061511
    Abstract: A computing device with multi-layer control: mentor layer and instruction/control layer includes a memory and one or more functional units. The computing device is configured to implement a multi-layer control structure including a data structure layer including a local high speed memory, a mentor layer, and an instruction/control layer. The local high speed memory includes one or more variables. The mentor layer includes one or more mentor circuits. The mentor circuits control actions associated with the Variables in the local high speed memory. The instruction/control layer includes one or more control circuits that interpret instructions or control operations by one or more functional units. In some embodiments, the local high speed memory implements a frame/bins structure. In some embodiments plural information is included in HLL and/or machine language.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: August 28, 2018
    Inventor: Hanan Potash
  • Patent number: 9984186
    Abstract: An electronic computer-aided design tool includes a design module and a printed electronics printer coupled to the design module. The design module determines one or more design specifications for an electronic device. The printed electronics printer produces one or more printed electronics prototypes of the electronic device based at least in part on at least on at least one of the design specifications. In some embodiments, the electronic computer-aided design tool includes a prototype testing unit that tests prototypes made by the printed electronics printer.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: May 29, 2018
    Inventor: Hanan Potash
  • Patent number: 9977693
    Abstract: A computing device includes a memory storing one or more Variables, and information relating to the singular/plural nature of at least one variable and/or algorithm, one or more functional units (Language Unit). The functional units receive the singular/plural information and perform one or more operations using at least one of the Variables using the singular/plural information. In an embodiment, a method of computing with plural information includes storing, in a memory, one or more Variables, storing, in a memory, information relating to the singular/plural nature of at least one algorithm; receiving at least a portion of the singular/plural information; and performing, using the singular/plural information, one or more operations using at least one of the Variables. In one embodiment, a method of computing includes linguistically implementing, by one or more circuits, plural-form instructions comprising one or more threads. Each thread may be a set of one or more programs.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: May 22, 2018
    Inventor: Hanan Potash
  • Publication number: 20170308405
    Abstract: A computing device includes one or more processors and one or more memory devices. The computing device comprises a Civilware tier configured to perform one or more resource management functions in the computing device. In some embodiments, the Civilware tier includes a resource manager that is at least partially programmable to manage one or more functions in the computing device. The Civilware tier may enforce one or more rules of behavior in the computing device. In some embodiments, the computing device further includes an instructions interpretation tier. The rules enforced by the Civilware tier are independent of the specifics of the algorithms executed in the instruction interpretation tier (e.g., the Civilware tier is orthogonal to the instruction interpretation tier).
    Type: Application
    Filed: April 26, 2016
    Publication date: October 26, 2017
    Inventor: Hanan Potash
  • Publication number: 20170242944
    Abstract: An electronic computer-aided design tool includes a design module and a printed electronics printer coupled to the design module. The design module determines one or more design specifications for an electronic device. The printed electronics printer produces one or more printed electronics prototypes of the electronic device based at least in part on at least on at least one of the design specifications. In some embodiments, the electronic computer-aided design tool includes a prototype testing unit that tests prototypes made by the printed electronics printer.
    Type: Application
    Filed: February 19, 2016
    Publication date: August 24, 2017
    Inventor: Hanan Potash
  • Publication number: 20170083464
    Abstract: A computing device includes a main memory; a local high speed memory; one or more functional units, one or more interconnects between the main memory and the local high speed memory, and one or more interconnects between the local high speed memory and the one or more functional units. The local high speed memory implements a frames/bins structure. The local high speed memory includes a plurality of frames, each of at least two of the frames comprising a physical memory element; and a plurality of bins distributed in the plurality of frames. Each of the bins includes a logical element. The functional units perform operations relating to Variables stored in the bins, each of the Variables including one or more words.
    Type: Application
    Filed: September 23, 2015
    Publication date: March 23, 2017
    Inventor: Hanan Potash
  • Publication number: 20170083434
    Abstract: A computer processor includes an operands-mapped namespace and/or a Variables mapped namespace. In some embodiments, a system for performing computing operations includes a processor comprising a namespace; and one or more memory devices physically or logically connected to the processor, wherein the memory devices comprise memory space. The namespace of the processor is not limited to the memory space of the one or more memory devices. In an embodiment, a method of computing includes physically or logically connecting a processor to one or more memory devices comprising memory space, and implementing, by the processor, a namespace, in which the namespace is not limited to the memory space to which the memory space is physically or logically connected.
    Type: Application
    Filed: September 23, 2015
    Publication date: March 23, 2017
    Inventor: Hanan Potash
  • Publication number: 20170083449
    Abstract: A computing device includes a memory structure storing one or more Variables; and a logical mentor. The logical mentor is assigned to at least one of the one or more Variables and performs addressing operations with respect to the Variables to which it is assigned. In an embodiment, a method of computing includes storing one or more Variables in the memory of a computing device, assigning a logical mentor to the Variables; and performing, by the logical mentor, addressing operations with respect to the Variables.
    Type: Application
    Filed: September 23, 2015
    Publication date: March 23, 2017
    Inventor: Hanan Potash
  • Publication number: 20170083238
    Abstract: A computing device includes a memory storing one or more Variables, and information relating to the singular/plural nature of at least one variable and/or algorithm, one or more functional units (Language Unit). The functional units receive the singular/plural information and perform one or more operations using at least one of the Variables using the singular/plural information. In an embodiment, a method of computing with plural information includes storing, in a memory, one or more Variables, storing, in a memory, information relating to the singular/plural nature of at least one algorithm; receiving at least a portion of the singular/plural information; and performing, using the singular/plural information, one or more operations using at least one of the Variables. In one embodiment, a method of computing includes linguistically implementing, by one or more circuits, plural-form instructions comprising one or more threads. Each thread may be a set of one or more programs.
    Type: Application
    Filed: September 23, 2015
    Publication date: March 23, 2017
    Inventor: Hanan Potash
  • Publication number: 20170083237
    Abstract: A computing device with multi-layer control: mentor layer and instruction/control layer includes a memory and one or more functional units. The computing device is configured to implement a multi-layer control structure including a data structure layer including a local high speed memory, a mentor layer, and an instruction/control layer. The local high speed memory includes one or more variables. The mentor layer includes one or more mentor circuits. The mentor circuits control actions associated with the Variables in the local high speed memory. The instruction/control layer includes one or more control circuits that interpret instructions or control operations by one or more functional units. In some embodiments, the local high speed memory implements a frame/bins structure. In some embodiments plural information is included in HLL and/or machine language.
    Type: Application
    Filed: September 23, 2015
    Publication date: March 23, 2017
    Inventor: Hanan Potash
  • Publication number: 20020154647
    Abstract: A method and system are presented for a frame handler, interfacing a SONET communications network to a computer processor. The highly parallel architecture of the frame handler allows it to operate in non-blocking mode—i.e., it can perform add/drop modifications to an incoming frame and begin re-transmission of the frame before the last incoming byte is received. This reduces latency to much less than that of a conventional frame handler, which must buffer the entire frame before re-transmitting it. Furthermore, the cost of the frame handler is reduced, since there is no requirement for large amounts of high-speed memory in which to store the frame. The frame handler is configurable to handle various STS-n frame sizes, and communication protocols.
    Type: Application
    Filed: February 16, 2001
    Publication date: October 24, 2002
    Inventor: Hanan Potash