Abstract: Disclosed is a digital computer which includes means for storing a plurality of instructions arranged as a program with conditional branch instructions at respective locations in said program specifying conditions to be tested; an instruction prefetch means and an instruction execute means for respectively fetching and executing different instructions of said program at the same time in a pipelined fashion; said conditional branch instruction at each of said locations further having multiple encodings which predict the state of the condition to be tested; and a control means for detecting when said prefetch means has fetched one of said conditional branch instructions and for fetching the next instruction based on the predicted state of the condition to be tested and encoded in said fetched conditional branch instruction.

Abstract: A digital system includes a digital bus, a sending device coupled to the bus for sending digital data words over the bus, and a receiving device coupled to the bus spaced apart from the sending device for receiving the sent words. Included in the receiving device is a storage circuit for temporarily storing multiple words from the sending device and a circuit for transmitting a response signal to the sending device each time a word is removed from the storage circuit. Included in the sending device is a control circuit for temporarily suspending the sending of the words over the bus whenever the number of words sent to the receiving device minus the number of response signals from the receiving device equals a predetermined number.

Abstract: A digital device time-multiplexes the execution of multiple tasks that are defined by respective sequences of control words in a control memory. In this device, the time-multiplexing is performed by sending control signals that are representative of respective resume addresses along with each output message sent by the device that calls for a response. These response messages are thereafter received by the device along with the control signals that were sent with the corresponding output message. Received response messages are thereafter operated on by the device by executing control words in the control memory beginning at the resume address represented by the received control signals.

Abstract: Disclosed is a digital computer whose structure is programmable. As a result, the computer's data section, which transforms operands in response to control word sequences, can be readily changed to interpret different types of control words. This is to be distinguished from merely changing the sequence of some fixed set of control words in a control memory. The disclosed programmable structure also enables the computer's control section, which generates the control word sequences, to be readily modified to perform different types of branches as opposed to branches of some rigidly fixed set.

Abstract: Disclosed is a circuit for transforming digital input signals representing several digits within a binary coded decimal (BCD) address into digital output signals for addressing a binarily addressable memory. One portion of the circuit concatenates the three least significant bits of each digit of those input signals whose most significant bit is a logical "0", and concatenates only the least significant bit of each digit of those input signals whose most significant bit is a logical "1". Another portion of the circuit simultaneously generates a predetermined code that is representative of the most significant bits of all of the digits of the input signals.

Abstract: Disclosed is a digital device on a semiconductor chip, which is comprised of a plurality of storage means for storing digital signals therein, a plurality of functional means for performing functional operations on the digital signals, and an interconnect matrix. The matrix includes a plurality of input busses connected to receive signals from the storage means and the functional means, and a plurality of output busses connected to send signals to the storage means and functional means. The interconnect matrix further includes N sets of selectable electrical contacts where N is any positive integer. Each set selectively intercouples the input busses to the output busses in various parallel paths. Signals are transferred between the input and output busses through any one set of the N sets of electrical contacts in response to N respective control signals.