Patents by Inventor Handoko Linewih

Handoko Linewih has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12176048
    Abstract: A one-time programmable (OTP) fuse includes a fuse link including a thin film resistor (TFR) layer between a first insulator layer and a second insulator layer. A first terminal of the OTP fuse includes a first conductive pillar through one of the first and second insulator layers and in contact with the TFR layer; and a second terminal of the OTP fuse includes a second conductive pillar through one of the first and second insulator layers and in contact with the TFR layer. The second conductive pillar and the TFR layer have a lateral contact interface having a same shape as an outer portion of the second conductive pillar. The second conductive pillar does not simply land on the TFR layer, but extends through it. Application of a current to the OTP fuse results in programming via rupture of the lateral contact interface (not electromigration in the fuse link).
    Type: Grant
    Filed: December 22, 2022
    Date of Patent: December 24, 2024
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Siow Lee Chwa, Handoko Linewih, Yudi Setiawan, Qiying Wong
  • Publication number: 20240421074
    Abstract: An apparatus includes a resistor structure within a back end of line (BEOL) via level. The resistor structure includes a lower resistor film, a first insulating layer over the lower resistor film, an upper resistor film over the first insulating layer, and a second insulating layer over the upper resistor film. First and second upper metal lines are above the second insulating layer, a first end of the upper resistor film is coupled to the first upper metal line by a first upper via or contact, and a second end of the upper resistor film is coupled to the second upper metal line by a second upper via or contact. The apparatus may be a resistor or a thermistor of a semiconductor device.
    Type: Application
    Filed: June 16, 2023
    Publication date: December 19, 2024
    Inventors: Qiying WONG, Handoko LINEWIH, Phyllis Shi Ya LIM, Chen Wai Samuel CHOW, Yudi SETIAWAN
  • Publication number: 20240212770
    Abstract: A one-time programmable (OTP) fuse includes a fuse link including a thin film resistor (TFR) layer between a first insulator layer and a second insulator layer. A first terminal of the OTP fuse includes a first conductive pillar through one of the first and second insulator layers and in contact with the TFR layer; and a second terminal of the OTP fuse includes a second conductive pillar through one of the first and second insulator layers and in contact with the TFR layer. The second conductive pillar and the TFR layer have a lateral contact interface having a same shape as an outer portion of the second conductive pillar. The second conductive pillar does not simply land on the TFR layer, but extends through it. Application of a current to the OTP fuse results in programming via rupture of the lateral contact interface (not electromigration in the fuse link).
    Type: Application
    Filed: December 22, 2022
    Publication date: June 27, 2024
    Inventors: Siow Lee Chwa, Handoko Linewih, Yudi Setiawan, Qiying Wong
  • Patent number: 11942415
    Abstract: A device may include a substrate, and an interlevel dielectric arranged over the substrate. The interlevel dielectric may include a first interlevel dielectric layer in an interconnect level i, the first interlevel dielectric layer having a first interconnect and a second interconnect therein. A nitride block insulator may be arranged over the first interlevel dielectric layer and over the first interconnect and the second interconnect. An opening may be arranged in the nitride block insulator, the opening extending through the nitride block insulator to expose a surface of the first interconnect in the first interlevel dielectric layer. A contact plug may be arranged in the opening of the nitride block insulator. The contact plug at least lines the opening and prevents out-diffusion of conductive material from the first interconnect. A thin film of a passive component may be arranged over the nitride block insulator and over the contact plug.
    Type: Grant
    Filed: August 16, 2022
    Date of Patent: March 26, 2024
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Handoko Linewih, Chor Shu Cheng, Tze Ho Simon Chan, Yudi Setiawan
  • Publication number: 20240021716
    Abstract: Structures including compound semiconductor-based devices and silicon-based devices integrated on a semiconductor substrate and methods of forming such structures. The structure comprises a layer stack on a substrate, a conductive contact extending in a vertical direction fully through the layer stack to the substrate, and a device structure including a source ohmic contact and a drain ohmic contact. The layer stack including a plurality of semiconductor layers each comprising a compound semiconductor material, the conductive contact is arranged in the layer stack to separate a first portion of the layer stack from a second portion of the layer stack, and the source ohmic contact and the drain ohmic contact have a contacting relationship with at least one of the plurality of semiconductor layers of the first portion of the layer stack.
    Type: Application
    Filed: July 14, 2022
    Publication date: January 18, 2024
    Inventors: Lawrence Selvaraj Susai, Handoko Linewih, Francois Hebert, Hendro Mario, Siow Lee Chwa
  • Publication number: 20240006529
    Abstract: Structures for a laterally-diffused metal-oxide-semiconductor device and methods of forming a structure for a laterally-diffused metal-oxide-semiconductor device. The structure comprises a semiconductor substrate including a first well, a second well positioned within the first well, a source region positioned in the first well, and a drain region positioned in the second well. The first well has a first conductivity type, and the second well, the source region, and the drain region have a second conductivity type opposite to the first conductivity type. The structure further comprises a field plate over the semiconductor substrate and a contact connecting the field plate to the drain region. The field plate is positioned to overlap with the drain region and with a portion of the second well adjacent to the drain region. The contact and the field plate comprise the same metal.
    Type: Application
    Filed: June 29, 2022
    Publication date: January 4, 2024
    Inventors: Surya Kris Amethystna, Guowei Zhang, Handoko Linewih, Jerry Joseph James
  • Publication number: 20230361127
    Abstract: Structures including III-V compound semiconductor-based devices and silicon-based devices integrated on a semiconductor substrate and methods of forming such structures. The structure includes a substrate having a device layer, a handle substrate, and a buried insulator layer between the handle substrate and the device layer. The structure includes a first semiconductor layer on the device layer in a first device region, and a second semiconductor layer on the device layer in a second device region. The first semiconductor layer contains a III-V compound semiconductor material, and the second semiconductor layer contains silicon. A first device structure includes a gate structure on the first semiconductor layer, and a second device structure includes a doped region in the second semiconductor layer. The doped region and the second semiconductor layer define a p-n junction.
    Type: Application
    Filed: April 27, 2023
    Publication date: November 9, 2023
    Inventors: Francois Hebert, Handoko Linewih
  • Patent number: 11784189
    Abstract: Structures including III-V compound semiconductor-based devices and silicon-based devices integrated on a semiconductor substrate and methods of forming such structures. The structure includes a substrate having a device layer, a handle substrate, and a buried insulator layer between the handle substrate and the device layer. The structure includes a first semiconductor layer on the device layer in a first device region, and a second semiconductor layer on the device layer in a second device region. The first semiconductor layer contains a III-V compound semiconductor material, and the second semiconductor layer contains silicon. A first device structure includes a gate structure on the first semiconductor layer, and a second device structure includes a doped region in the second semiconductor layer. The doped region and the second semiconductor layer define a p-n junction.
    Type: Grant
    Filed: August 20, 2021
    Date of Patent: October 10, 2023
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Francois Hebert, Handoko Linewih
  • Patent number: 11688785
    Abstract: A semiconductor device is provided. The semiconductor device comprises a substrate having a first surface and a second surface, the substrate comprising a wide bandgap semiconductor material. An epitaxial layer is on the first surface of the substrate and a metal germanosilicide layer is above the second surface of the substrate. The metal germanosilicide layer forms an ohmic contact to the substrate.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: June 27, 2023
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Yudi Setiawan, Handoko Linewih
  • Publication number: 20230197320
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heat dissipating structures and methods of manufacture. The structure includes: a thin film resistor within a back end of the line structure; and a heat dissipating structure below the thin film resistor, the heat dissipating structure includes a top plate with a slotted configuration and being within the back end of the line structure.
    Type: Application
    Filed: December 17, 2021
    Publication date: June 22, 2023
    Inventors: Yudi SETIAWAN, Handoko LINEWIH, Siow Lee CHWA
  • Patent number: 11637100
    Abstract: The present disclosure generally relates to a semiconductor device having a capacitor and a resistor and a method of forming the same. More particularly, the present disclosure relates to a metal-insulator-metal (MIM) capacitor and a thin film resistor (TFR) formed in a back end of line portion of an integrated circuit (IC) chip.
    Type: Grant
    Filed: August 11, 2021
    Date of Patent: April 25, 2023
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Qiying Wong, Handoko Linewih, Yudi Setiawan, Chengang Feng, Siow Lee Chwa
  • Publication number: 20230059665
    Abstract: Structures including III-V compound semiconductor-based devices and silicon-based devices integrated on a semiconductor substrate and methods of forming such structures. The structure includes a substrate having a device layer, a handle substrate, and a buried insulator layer between the handle substrate and the device layer. The structure includes a first semiconductor layer on the device layer in a first device region, and a second semiconductor layer on the device layer in a second device region. The first semiconductor layer contains a III-V compound semiconductor material, and the second semiconductor layer contains silicon. A first device structure includes a gate structure on the first semiconductor layer, and a second device structure includes a doped region in the second semiconductor layer. The doped region and the second semiconductor layer define a p-n junction.
    Type: Application
    Filed: August 20, 2021
    Publication date: February 23, 2023
    Inventors: Francois Hebert, Handoko Linewih
  • Publication number: 20230046455
    Abstract: The present disclosure generally relates to a semiconductor device having a capacitor and a resistor and a method of forming the same. More particularly, the present disclosure relates to a metal-insulator-metal (MIM) capacitor and a thin film resistor (TFR) formed in a back end of line portion of an integrated circuit (IC) chip.
    Type: Application
    Filed: August 11, 2021
    Publication date: February 16, 2023
    Inventors: QIYING WONG, HANDOKO LINEWIH, YUDI SETIAWAN, CHENGANG FENG, SIOW LEE CHWA
  • Patent number: 11545570
    Abstract: The present disclosure generally to semiconductor devices, and more particularly to semiconductor devices having high-voltage transistors integrated on a semiconductor-on-insulator substrate and methods of forming the same. The present disclosure provides a semiconductor device including a semiconductor-on-insulator (SOI) substrate having a semiconductor layer, a bulk substrate and an insulating layer between the semiconductor layer and the bulk substrate, a source region and a drain region disposed on the bulk substrate, an isolation structure extending through the insulating layer and the semiconductor layer and terminates in the bulk substrate, and a gate structure between the source region and the drain region, the gate structure is disposed on the semiconductor layer.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: January 3, 2023
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Pinghui Li, Handoko Linewih, Darin Arthur Chan, Ruchil Kumar Jain
  • Patent number: 11545486
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an integrated thin film resistor with a metal-insulator-metal capacitor and methods of manufacture. The structure includes: a first buffer contact on a substrate; a second buffer contact on the substrate, the second buffer contact being on a same wiring level as the first buffer contact; a resistive film contacting the first buffer contact and the second buffer contact, the resistive film extending on the substrate between the first buffer contact and the second buffer contact; and electrical contacts landing on both the first buffer contact and the second buffer contact, but not directly contacting with the resistive film.
    Type: Grant
    Filed: October 2, 2020
    Date of Patent: January 3, 2023
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Chengang Feng, Yanxia Shao, Yudi Setiawan, Handoko Linewih, Xuesong Rao
  • Publication number: 20220392837
    Abstract: A device may include a substrate, and an interlevel dielectric arranged over the substrate. The interlevel dielectric may include a first interlevel dielectric layer in an interconnect level i, the first interlevel dielectric layer having a first interconnect and a second interconnect therein. A nitride block insulator may be arranged over the first interlevel dielectric layer and over the first interconnect and the second interconnect. An opening may be arranged in the nitride block insulator, the opening extending through the nitride block insulator to expose a surface of the first interconnect in the first interlevel dielectric layer. A contact plug may be arranged in the opening of the nitride block insulator. The contact plug at least lines the opening and prevents out-diffusion of conductive material from the first interconnect. A thin film of a passive component may be arranged over the nitride block insulator and over the contact plug.
    Type: Application
    Filed: August 16, 2022
    Publication date: December 8, 2022
    Inventors: Handoko LINEWIH, Chor Shu CHENG, Tze Ho Simon CHAN, Yudi SETIAWAN
  • Patent number: 11437406
    Abstract: A semiconductor device may be provided, including a substrate which includes a first semiconductor layer having a well region arranged within the first semiconductor layer, a buried insulator layer arranged over the first semiconductor layer, and a second semiconductor layer arranged over the buried insulator layer. The semiconductor device may include a capacitive structure including: the well region, at least one contact to the well region, at least a portion of the buried insulator layer over the well region, at least a portion of the second semiconductor layer, a source region and a drain region arranged over the second semiconductor layer, a gate dielectric layer arranged over the second semiconductor layer and arranged laterally between the source region and the drain region, and a gate layer arranged over the gate dielectric layer. The well region, the source region, and the drain region may have the same conductivity type.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: September 6, 2022
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Phyllis Shi Ya Lim, Handoko Linewih, Shu Zhong, Chor Shu Cheng
  • Publication number: 20220181479
    Abstract: A semiconductor device is provided. The semiconductor device comprises a substrate having a wide bandgap semiconductor material and an epitaxial layer arranged over a first surface of the substrate. A source region having a first conductivity type may be arranged in the epitaxial layer. A well region having a second conductivity type may be laterally adjacent to the source region. The first conductivity type may be different from the second conductivity type. A gate dielectric layer may be arranged over the well region. A field dielectric layer may be arranged over the epitaxial layer adjacent to the well region.
    Type: Application
    Filed: December 8, 2020
    Publication date: June 9, 2022
    Inventors: CHOR SHU CHENG, HANDOKO LINEWIH, SIOW LEE CHWA
  • Publication number: 20220108980
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an integrated thin film resistor with a metal-insulator-metal capacitor and methods of manufacture. The structure includes: a first buffer contact on a substrate; a second buffer contact on the substrate, the second buffer contact being on a same wiring level as the first buffer contact; a resistive film contacting the first buffer contact and the second buffer contact, the resistive film extending on the substrate between the first buffer contact and the second buffer contact; and electrical contacts landing on both the first buffer contact and the second buffer contact, but not directly contacting with the resistive film.
    Type: Application
    Filed: October 2, 2020
    Publication date: April 7, 2022
    Inventors: Chengang FENG, Yanxia SHAO, Yudi SETIAWAN, Handoko LINEWIH, Xuesong RAO
  • Publication number: 20210305391
    Abstract: A semiconductor device is provided. The semiconductor device comprises a substrate having a first surface and a second surface, the substrate comprising a wide bandgap semiconductor material. An epitaxial layer is on the first surface of the substrate and a metal germanosilicide layer is above the second surface of the substrate. The metal germanosilicide layer forms an ohmic contact to the substrate.
    Type: Application
    Filed: March 26, 2020
    Publication date: September 30, 2021
    Inventors: YUDI SETIAWAN, HANDOKO LINEWIH