Patents by Inventor Handoko Linewih
Handoko Linewih has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210305391Abstract: A semiconductor device is provided. The semiconductor device comprises a substrate having a first surface and a second surface, the substrate comprising a wide bandgap semiconductor material. An epitaxial layer is on the first surface of the substrate and a metal germanosilicide layer is above the second surface of the substrate. The metal germanosilicide layer forms an ohmic contact to the substrate.Type: ApplicationFiled: March 26, 2020Publication date: September 30, 2021Inventors: YUDI SETIAWAN, HANDOKO LINEWIH
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Publication number: 20210210630Abstract: The present disclosure generally to semiconductor devices, and more particularly to semiconductor devices having high-voltage transistors integrated on a semiconductor-on-insulator substrate and methods of forming the same. The present disclosure provides a semiconductor device including a semiconductor-on-insulator (SOI) substrate having a semiconductor layer, a bulk substrate and an insulating layer between the semiconductor layer and the bulk substrate, a source region and a drain region disposed on the bulk substrate, an isolation structure extending through the insulating layer and the semiconductor layer and terminates in the bulk substrate, and a gate structure between the source region and the drain region, the gate structure is disposed on the semiconductor layer.Type: ApplicationFiled: January 8, 2020Publication date: July 8, 2021Inventors: PINGHUI LI, HANDOKO LINEWIH, DARIN ARTHUR CHAN, RUCHIL KUMAR JAIN
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Patent number: 11056430Abstract: According to various embodiments, a semiconductor device may include a thin film arranged within a first inter-level dielectric layer, a masking region, and a contact plug. The masking region may be arranged over the thin film, within the first inter-level dielectric layer. The masking region may be structured to have a higher etch rate than the first inter-level dielectric layer. The contact plug may extend along a vertical axis, from a second inter-level dielectric layer to the thin film. A bottom portion of the contact plug may be surrounded by the masking region. The bottom portion of the contact plug may include a lateral member that extends along a horizontal plane at least substantially perpendicular to the vertical axis. The lateral member may be in contact with the thin film.Type: GrantFiled: March 10, 2020Date of Patent: July 6, 2021Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Chengang Feng, Handoko Linewih, Yanxia Shao, Yudi Setiawan
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Publication number: 20210193692Abstract: A semiconductor device may be provided, including a substrate which includes a first semiconductor layer having a well region arranged within the first semiconductor layer, a buried insulator layer arranged over the first semiconductor layer, and a second semiconductor layer arranged over the buried insulator layer. The semiconductor device may include a capacitive structure including: the well region, at least one contact to the well region, at least a portion of the buried insulator layer over the well region, at least a portion of the second semiconductor layer, a source region and a drain region arranged over the second semiconductor layer, a gate dielectric layer arranged over the second semiconductor layer and arranged laterally between the source region and the drain region, and a gate layer arranged over the gate dielectric layer. The well region, the source region, and the drain region may have the same conductivity type.Type: ApplicationFiled: December 20, 2019Publication date: June 24, 2021Inventors: Phyllis Shi Ya LIM, Handoko LINEWIH, Shu ZHONG, Chor Shu CHENG
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Publication number: 20210098363Abstract: A device may include a substrate, and an interlevel dielectric arranged over the substrate. The interlevel dielectric may include a first interlevel dielectric layer in an interconnect level i, the first interlevel dielectric layer having a first interconnect and a second interconnect therein. A nitride block insulator may be arranged over the first interlevel dielectric layer and over the first interconnect and the second interconnect. An opening may be arranged in the nitride block insulator, the opening extending through the nitride block insulator to expose a surface of the first interconnect in the first interlevel dielectric layer. A contact plug may be arranged in the opening of the nitride block insulator. The contact plug at least lines the opening and prevents out-diffusion of conductive material from the first interconnect. A thin film of a passive component may be arranged over the nitride block insulator and over the contact plug.Type: ApplicationFiled: September 30, 2019Publication date: April 1, 2021Inventors: Handoko LINEWIH, Chor Shu CHENG, Tze Ho Simon CHAN, Yudi SETIAWAN
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Patent number: 10651166Abstract: E-fuse cells and methods for protecting e-fuses are provided. An exemplary e-fuse cell includes an e-fuse having a first end coupled to a source node and a second end selectively coupled to a ground. Further, the exemplary e-fuse includes a selectively activated shunt path from the source node to the ground. Also, the exemplary e-fuse includes a device for activating the shunt path in response to an electrical overstress event.Type: GrantFiled: May 31, 2017Date of Patent: May 12, 2020Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Handoko Linewih, Chien-Hsin Lee
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Patent number: 10298215Abstract: Integrated circuits (ICs) include electrostatic discharge protection including a transistor having a drain operably coupled to a first rail of the integrated circuit and a source operatively coupled to a second rail of the integrated circuit. A voltage regulating trigger circuit is operatively coupled to the first rail and to a gate of the transistor to turn on of the transistor responsive to an ESD event affecting the integrated circuit, wherein the voltage regulating trigger circuit limits a potential of the first rail to a first potential and a gate potential of the transistor to a second potential, less than the first potential but sufficient to turn the transistor on to conduct current arising from the ESD event from the first rail to the second rail.Type: GrantFiled: April 19, 2016Date of Patent: May 21, 2019Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Wei Gao, Yi Lu, Handoko Linewih
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Publication number: 20180350796Abstract: E-fuse cells and methods for protecting e-fuses are provided. An exemplary e-fuse cell includes an e-fuse having a first end coupled to a source node and a second end selectively coupled to a ground. Further, the exemplary e-fuse includes a selectively activated shunt path from the source node to the ground. Also, the exemplary e-fuse includes a device for activating the shunt path in response to an electrical overstress event.Type: ApplicationFiled: May 31, 2017Publication date: December 6, 2018Inventors: Handoko Linewih, Chien-Hsin Lee
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Patent number: 10121779Abstract: Integrated circuits and methods of producing integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a source and a drain defined within a body isolation well. A gate overlies the body isolation well between the source and the drain, and an isolating structure is formed within the body isolation well. The isolating structure sections the source into a plurality of source sections with the plurality of source sections adjacent to one gate.Type: GrantFiled: December 13, 2016Date of Patent: November 6, 2018Assignee: Globalfoundries Singapore Pte. Ltd.Inventors: Handoko Linewih, Chao Cheng
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Publication number: 20180166438Abstract: Integrated circuits and methods of producing integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a source and a drain defined within a body isolation well. A gate overlies the body isolation well between the source and the drain, and an isolating structure is formed within the body isolation well. The isolating structure sections the source into a plurality of source sections with the plurality of source sections adjacent to one gate.Type: ApplicationFiled: December 13, 2016Publication date: June 14, 2018Inventors: Handoko Linewih, Chao Cheng
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Publication number: 20180083440Abstract: Integrated circuits with electrostatic discharge (ESD) protection and methods of providing ESD protection in an integrated circuit are provided, which include an ability to off-chip disable/enable the ESD protection. An ESD Protection Circuit incorporates a disable/enable device coupled to the ESD protection circuit. The disable/enable is addressable from a pin out, e.g., an ESD disable/enable pin of the IC package.Type: ApplicationFiled: September 19, 2016Publication date: March 22, 2018Inventors: Wei Gao, Handoko Linewih
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Patent number: 9870939Abstract: Devices and methods of forming an integrated circuit (IC) that offer protection against ESD in high voltage (HV) circuit applications are disclosed. A device includes N ones of a field effect transistor (FET) stacked in series to provide an N-level stack, where N is an integer greater than 1. A first pad of the device is coupled to a first FET and a second pad is coupled to an Nth FET. The device also includes a stacked/distributed RC control circuit configured to cause a short circuit between the first pad and the second pad in response to an ESD event. During the ESD event, the RC control circuit is configured to concurrently provide sufficient voltage to control the N ones of the FET by turning them on using parasitic conduction to cause the short circuit.Type: GrantFiled: August 28, 2015Date of Patent: January 16, 2018Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Handoko Linewih, Ming Li, Sevashanmugam Marimuthu, Ronghua Yu
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Publication number: 20170302066Abstract: Integrated circuits (ICs) include electrostatic discharge protection including a transistor having a drain operably coupled to a first rail of the integrated circuit and a source operatively coupled to a second rail of the integrated circuit. A voltage regulating trigger circuit is operatively coupled to the first rail and to a gate of the transistor to turn on of the transistor responsive to an ESD event affecting the integrated circuit, wherein the voltage regulating trigger circuit limits a potential of the first rail to a first potential and a gate potential of the transistor to a second potential, less than the first potential but sufficient to turn the transistor on to conduct current arising from the ESD event from the first rail to the second rail.Type: ApplicationFiled: April 19, 2016Publication date: October 19, 2017Inventors: Wei Gao, Yi Lu, Handoko Linewih
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Publication number: 20160155737Abstract: Devices and methods of forming an integrated circuit (IC) that offer protection against ESD in high voltage (HV) circuit applications are disclosed. A device includes N ones of a field effect transistor (FET) stacked in series to provide an N-level stack, where N is an integer greater than 1. A first pad of the device is coupled to a first FET and a second pad is coupled to an Nth FET. The device also includes a stacked/distributed RC control circuit configured to cause a short circuit between the first pad and the second pad in response to an ESD event. During the ESD event, the RC control circuit is configured to concurrently provide sufficient voltage to control the N ones of the FET by turning them on using parasitic conduction to cause the short circuit.Type: ApplicationFiled: August 28, 2015Publication date: June 2, 2016Inventors: Handoko LINEWIH, Ming LI, Sevashanmugam MARIMUTHU, Ronghua YU
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Patent number: 8913359Abstract: An RC-based electrostatic discharge protection device provides an extended snapback trigger voltage range, thereby avoiding latch-up. Two parallel current discharge paths are provided between supply terminals during an electrostatic discharge event by virtue of an added external resistor. The first current discharge path includes body resistance of the protection device and the second current discharge path includes the external resistor.Type: GrantFiled: December 11, 2012Date of Patent: December 16, 2014Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Da-Wei Lai, Ying-Chang Lin, Handoko Linewih
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Patent number: 8891215Abstract: A triple stack NMOS integrated circuit structure protection circuit for a plurality of terminals operative at respective voltage levels is coupled between the plurality of terminals. First and second NMOS elements of the triple stack NMOS share a common active region. A third NMOS element, vertically positioned with respect to the first and second NMOS elements, has an active region separate from the active region of the first and second NMOS elements. The first, second and third NMOS elements are connected in series between two terminals of the plurality of terminals.Type: GrantFiled: December 11, 2012Date of Patent: November 18, 2014Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Da-Wei Lai, Handoko Linewih, Ying-Chang Lin
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Patent number: 8853784Abstract: A device having a substrate defined with a device region which includes an ESD protection circuit is disclosed. The ESD protection circuit has first and second transistors. A transistor includes a gate having first and second sides, a first diffusion region in the device region adjacent to the first side of the gate, and a second diffusion region in the device region displaced away from the second side of the gate. The first and second diffusion regions include dopants of a first polarity type. The device includes a first device well which encompasses the device region and second device wells which are disposed within the first device well. A well contact is coupled to the second device wells. The well contact surrounds the gates of the transistors and abuts the first diffusion regions of the transistors.Type: GrantFiled: January 10, 2013Date of Patent: October 7, 2014Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Da-Wei Lai, Handoko Linewih, Ying-Chang Lin
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Patent number: 8847318Abstract: A device which includes a substrate defined with a device region with an ESD protection circuit having at least first and second transistors is disclosed. Each of the transistors includes a gate having first and second sides, a first diffusion region in the device region adjacent to the first side of the gate, a second diffusion region in the device region displaced away from the second side of the gate, and a drift isolation region disposed between the gate and the second diffusion region. A first device well encompasses the device region and a second device well is disposed within the first device well. The device also includes a drift well which encompasses the second diffusion region. Edges of the drift well do not extend below the gate and is away from a channel region. A drain well is disposed under the second diffusion region and within the drift well.Type: GrantFiled: March 14, 2013Date of Patent: September 30, 2014Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Da-Wei Lai, Handoko Linewih, Ying-Chang Lin
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Publication number: 20140160605Abstract: A triple stack NMOS integrated circuit structure protection circuit for a plurality of terminals operative at respective voltage levels is coupled between the plurality of terminals. First and second NMOS elements of the triple stack NMOS share a common active region. A third NMOS element, vertically positioned with respect to the first and second NMOS elements, has an active region separate from the active region of the first and second NMOS elements. The first, second and third NMOS elements are connected in series between two terminals of the plurality of terminals.Type: ApplicationFiled: December 11, 2012Publication date: June 12, 2014Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Da-Wei LAI, Handoko LINEWIH, Ying-Chang LIN
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Publication number: 20140160604Abstract: An RC-based electrostatic discharge protection device provides an extended snapback trigger voltage range, thereby avoiding latch-up. Two parallel current discharge paths are provided between supply terminals during an electrostatic discharge event by virtue of an added external resistor. The first current discharge path includes body resistance of the protection device and the second current discharge path includes the external resistor.Type: ApplicationFiled: December 11, 2012Publication date: June 12, 2014Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Da-Wei LAI, Ying-Chang LIN, Handoko LINEWIH