Patents by Inventor Handoko Linewih

Handoko Linewih has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Latch-up free ESD protection
    Patent number: 8710545
    Abstract: An ESD module having a first portion (FP) and a second portion (SP) in a substrate is presented. The FP includes a FP well of a second polarity type and first and second FP contact regions. The first FP contact region is of a first polarity type and the second FP contact region is of a second polarity type. The SP includes a SP well of a first polarity type and first and second SP contact regions. The first SP contact region is of a first polarity type and the second SP contact region is of a second polarity type. An intermediate portion (IP) is disposed in the substrate between the FP and SP in the substrate. The IP includes a well of the second polarity type. The IP increases trigger current and holding voltage of the module to prevent latch up during normal device operation.
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: April 29, 2014
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Da-Wei Lai, Handoko Linewih
  • LATCH-UP FREE ESD PROTECTION
    Publication number: 20130341675
    Abstract: An ESD module having a first portion (FP) and a second portion (SP) in a substrate is presented. The FP includes a FP well of a second polarity type and first and second FP contact regions. The first FP contact region is of a first polarity type and the second FP contact region is of a second polarity type. The SP includes a SP well of a first polarity type and first and second SP contact regions. The first SP contact region is of a first polarity type and the second SP contact region is of a second polarity type. An intermediate portion (IP) is disposed in the substrate between the FP and SP in the substrate. The IP includes a well of the second polarity type. The IP increases trigger current and holding voltage of the module to prevent latch up during normal device operation.
    Type: Application
    Filed: June 26, 2012
    Publication date: December 26, 2013
    Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Da-Wei LAI, Handoko LINEWIH
  • Integrated electronic disconnecting circuits, methods, and systems
    Patent number: 7262946
    Abstract: Merged devices for transient blocking. A pass transistor is placed so that its body potential drives the gate of a depletion-mode JFET-type blocking transistor. Thus a transient which appears on an external terminal is very rapidly propagated to shut off the blocking transistor, before large numbers of carriers can be injected. Preferably a shunt device is also used to drop high potentials which may appear at the same time. This connection can be particularly useful in power or data input terminals.
    Type: Grant
    Filed: August 23, 2004
    Date of Patent: August 28, 2007
    Assignee: FulTec Semiconductor, Inc.
    Inventors: Richard Harris, Handoko Linewih
  • Integrated electronic disconnecting circuits, methods, and systems
    Publication number: 20050152080
    Abstract: Merged devices for transient blocking. A pass transistor is placed so that its body potential drives the gate of a depletion-mode JFET-type blocking transistor. Thus a transient which appears on an external terminal is very rapidly propagated to shut off the blocking transistor, before large numbers of carriers can be injected. Preferably a shunt device is also used to drop high potentials which may appear at the same time. This connection can be particularly useful in power or data input terminals.
    Type: Application
    Filed: August 23, 2004
    Publication date: July 14, 2005
    Applicant: Fultec Semiconductor Inc.
    Inventors: Richard Harris, Handoko Linewih