Patents by Inventor HanGil Shin

HanGil Shin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10903183
    Abstract: A semiconductor device has a leadframe with a plurality of bodies extending from the base plate. A first semiconductor die is mounted to the base plate of the leadframe between the bodies. An encapsulant is deposited over the first semiconductor die and base plate and around the bodies of the leadframe. A portion of the encapsulant over the bodies of the leadframe is removed to form first openings in the encapsulant that expose the bodies. An interconnect structure is formed over the encapsulant and extending into the first openings to the bodies of the leadframe. The leadframe and bodies are removed to form second openings in the encapsulant corresponding to space previously occupied by the bodies to expose the interconnect structure. A second semiconductor die is mounted over the first semiconductor die with bumps extending into the second openings of the encapsulant to electrically connect to the interconnect structure.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: January 26, 2021
    Inventors: HeeJo Chi, NamJu Cho, HanGil Shin
  • Patent number: 10510703
    Abstract: A semiconductor device has a plurality of semiconductor die. A substrate is provided with bumps disposed over the substrate. A first prefabricated insulating film is disposed between the semiconductor die and substrate. An interconnect structure is formed over the semiconductor die and first prefabricated insulating film. The bumps include a copper core encapsulated within copper plating. The first prefabricated insulating film includes glass cloth, glass fiber, or glass fillers. The substrate includes a conductive layer formed in the substrate and coupled to the bumps. The semiconductor die is disposed between the bumps of the substrate. The bumps and the semiconductor die are embedded within the first prefabricated insulating film. A portion of the first prefabricated insulating film is removed to expose the bumps. The bumps electrically connect the substrate to the interconnect structure.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: December 17, 2019
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: HeeJo Chi, HanGil Shin, NamJu Cho
  • Patent number: 9966335
    Abstract: A semiconductor device has an interposer frame mounted over a carrier. A semiconductor die has an active surface and bumps formed over the active surface. The semiconductor die can be mounted within a die opening of the interposer frame or over the interposer frame. Stacked semiconductor die can also be mounted within the die opening of the interposer frame or over the interposer frame. Bond wires or bumps are formed between the semiconductor die and interposer frame. An encapsulant is deposited over the interposer frame and semiconductor die. An interconnect structure is formed over the encapsulant and bumps of the first semiconductor die. An electronic component, such as a discrete passive device, semiconductor die, or stacked semiconductor die, is mounted over the semiconductor die and interposer frame. The electronic component has an I/O count less than an I/O count of the semiconductor die.
    Type: Grant
    Filed: January 13, 2015
    Date of Patent: May 8, 2018
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: NamJu Cho, HeeJo Chi, HanGil Shin
  • Patent number: 9865575
    Abstract: Methods of forming conductive and insulating layers for semiconductor devices and packages. Substrate is provided with integrated circuit device and interconnect structure mounted thereon, the interconnect structure adjacent the integrated circuit device. The integrated circuit device and portions of the interconnect structure can be covered with an encapsulation exposing a portion of the interconnect structure. Conductive material is formed over the exposed portion of the interconnect structure by a depositing process followed by a heating process to alter the chemical properties of the conductive material. Optionally, a dispersing process may be incorporated.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: January 9, 2018
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: HeeJo Chi, HanGil Shin, KyungMoon Kim
  • Patent number: 9842808
    Abstract: A semiconductor device has a plurality of semiconductor die or components mounted over a carrier. A leadframe is mounted over the carrier between the semiconductor die. The leadframe has a plate and bodies extending from the plate. The bodies of the leadframe are disposed around a perimeter of the semiconductor die. An encapsulant is deposited over the carrier, leadframe, and semiconductor die. A plurality of conductive vias is formed through the encapsulant and electrically connected to the bodies of the leadframe and contact pads on the semiconductor die. An interconnect structure is formed over the encapsulant and electrically connected to the conductive vias. A first channel is formed through the interconnect structure, encapsulant, leadframe, and partially through the carrier. The carrier is removed to singulate the semiconductor die. A second channel is formed through the plate of the leadframe to physically separate the bodies of the leadframe.
    Type: Grant
    Filed: October 4, 2012
    Date of Patent: December 12, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: HanGil Shin, NamJu Cho, HeeJo Chi
  • Publication number: 20170250154
    Abstract: A semiconductor device has a plurality of semiconductor die. A substrate is provided with bumps disposed over the substrate. A first prefabricated insulating film is disposed between the semiconductor die and substrate. An interconnect structure is formed over the semiconductor die and first prefabricated insulating film. The bumps include a copper core encapsulated within copper plating. The first prefabricated insulating film includes glass cloth, glass fiber, or glass fillers. The substrate includes a conductive layer formed in the substrate and coupled to the bumps. The semiconductor die is disposed between the bumps of the substrate. The bumps and the semiconductor die are embedded within the first prefabricated insulating film. A portion of the first prefabricated insulating film is removed to expose the bumps. The bumps electrically connect the substrate to the interconnect structure.
    Type: Application
    Filed: May 12, 2017
    Publication date: August 31, 2017
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: HeeJo Chi, HanGil Shin, NamJu Cho
  • Patent number: 9748157
    Abstract: An integrated circuit packaging system and method of manufacture thereof includes: a base substrate having a bottom pad; an integrated circuit device mounted on the base substrate; an interposer having a package interconnect mounted on the base substrate, the package interconnect includes an underside base portion having an irregular surface characteristic of a coining process; and an encapsulation between the interposer and the base substrate.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: August 29, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: HeeJo Chi, HanGil Shin, NamJu Cho, Kyung Moon Kim
  • Patent number: 9691707
    Abstract: A semiconductor device has a plurality of semiconductor die. A substrate is provided with bumps disposed over the substrate. A first prefabricated insulating film is disposed between the semiconductor die and substrate. An interconnect structure is formed over the semiconductor die and first prefabricated insulating film. The bumps include a copper core encapsulated within copper plating. The first prefabricated insulating film includes glass cloth, glass fiber, or glass fillers. The substrate includes a conductive layer formed in the substrate and coupled to the bumps. The semiconductor die is disposed between the bumps of the substrate. The bumps and the semiconductor die are embedded within the first prefabricated insulating film. A portion of the first prefabricated insulating film is removed to expose the bumps. The bumps electrically connect the substrate to the interconnect structure.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: June 27, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: HeeJo Chi, HanGil Shin, NamJu Cho
  • Patent number: 9558965
    Abstract: A semiconductor wafer has a plurality of first semiconductor die. A second semiconductor die is mounted to the first semiconductor die. The active surface of the first semiconductor die is oriented toward an active surface of the second semiconductor die. An encapsulant is deposited over the first and second semiconductor die. A portion of a back surface of the second semiconductor die opposite the active surface is removed. Conductive pillars are formed around the second semiconductor die. TSVs can be formed through the first semiconductor die. An interconnect structure is formed over the back surface of the second semiconductor die, encapsulant, and conductive pillars. The interconnect structure is electrically connected to the conductive pillars. A portion of a back surface of the first semiconductor die opposite the active surface is removed. A heat sink or shielding layer can be formed over the back surface of the first semiconductor die.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: January 31, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: HeeJo Chi, NamJu Cho, HanGil Shin
  • Patent number: 9508635
    Abstract: Methods of forming conductive jumper traces for semiconductor devices and packages. Substrate is provided having first, second and third trace lines formed thereon, where the first trace line is between the second and third trace lines. The first trace line can be isolated with a covering layer. A conductive layer can be formed between the second and third trace lines and over the first trace line by a depositing process followed by a heating process to alter the chemical properties of the conductive layer. The resulting conductive layer is able to conform to the covering layer and serve to provide electrical connection between the second and third trace lines.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: November 29, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: HanGil Shin, HeeJo Chi, NamJu Cho
  • Patent number: 9496152
    Abstract: A method of manufacture of a carrier system includes: providing a carrier base; forming a recess in the carrier base with the recess around a planar surface; forming a first barrier on the planar surface; forming a second barrier on the carrier base in the recess; forming a first post on the first barrier; and forming a second post on the second barrier.
    Type: Grant
    Filed: March 12, 2010
    Date of Patent: November 15, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: NamJu Cho, HeeJo Chi, HanGil Shin
  • Publication number: 20160329310
    Abstract: Methods of forming conductive and insulating layers for semiconductor devices and packages. Substrate is provided with integrated circuit device and interconnect structure mounted thereon, the interconnect structure adjacent the integrated circuit device. The integrated circuit device and portions of the interconnect structure can be covered with an encapsulation exposing a portion of the interconnect structure. Conductive material is formed over the exposed portion of the interconnect structure by a depositing process followed by a heating process to alter the chemical properties of the conductive material. Optionally, a dispersing process may be incorporated.
    Type: Application
    Filed: July 5, 2016
    Publication date: November 10, 2016
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: HeeJo Chi, HanGil Shin, KyungMoon Kim
  • Publication number: 20160233168
    Abstract: A semiconductor device has a plurality of semiconductor die. A substrate is provided with bumps disposed over the substrate. A first prefabricated insulating film is disposed between the semiconductor die and substrate. An interconnect structure is formed over the semiconductor die and first prefabricated insulating film. The bumps include a copper core encapsulated within copper plating. The first prefabricated insulating film includes glass cloth, glass fiber, or glass fillers. The substrate includes a conductive layer formed in the substrate and coupled to the bumps. The semiconductor die is disposed between the bumps of the substrate. The bumps and the semiconductor die are embedded within the first prefabricated insulating film. A portion of the first prefabricated insulating film is removed to expose the bumps. The bumps electrically connect the substrate to the interconnect structure.
    Type: Application
    Filed: April 15, 2016
    Publication date: August 11, 2016
    Applicant: STATS ChipPAC, Ltd.
    Inventors: HeeJo Chi, HanGil Shin, NamJu Cho
  • Patent number: 9406533
    Abstract: Methods of forming conductive and insulating layers for semiconductor devices and packages. Substrate is provided with integrated circuit device and interconnect structure mounted thereon, the interconnect structure adjacent the integrated circuit device. The integrated circuit device and portions of the interconnect structure can be covered with an encapsulation exposing a portion of the interconnect structure. Conductive material is formed over the exposed portion of the interconnect structure by a depositing process followed by a heating process to alter the chemical properties of the conductive material. Optionally, a dispersing process may be incorporated.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: August 2, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: HeeJo Chi, HanGil Shin, KyungMoon Kim
  • Patent number: 9397050
    Abstract: A semiconductor wafer contains a plurality of semiconductor die. A plurality of bumps is formed on the semiconductor wafer. The bumps are electrically connected to contact pads on an active surface of the die. The bumps can also be pillars or stud bumps. A first encapsulant is deposited over the bumps. The semiconductor wafer is singulated to separate the die by cutting channels partially through the wafer and back grinding the wafer down to the channels. A second encapsulant is deposited over the die. A first interconnect structure is formed over a first surface of the second encapsulant. The first interconnect structure is electrically connected to the bumps. A second interconnect structure is formed over a second surface of the second encapsulant. Secondary semiconductor components can be stacked over the second interconnect structure. A third encapsulant is deposited over the stacked secondary components and second interconnect structure.
    Type: Grant
    Filed: August 31, 2009
    Date of Patent: July 19, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: HanGil Shin, HeeJo Chi, NamJu Cho
  • Patent number: 9362161
    Abstract: A semiconductor device has a plurality of semiconductor die. A substrate is provided with bumps disposed over the substrate. A first prefabricated insulating film is disposed between the semiconductor die and substrate. An interconnect structure is formed over the semiconductor die and first prefabricated insulating film. The bumps include a copper core encapsulated within copper plating. The first prefabricated insulating film includes glass cloth, glass fiber, or glass fillers. The substrate includes a conductive layer formed in the substrate and coupled to the bumps. The semiconductor die is disposed between the bumps of the substrate. The bumps and the semiconductor die are embedded within the first prefabricated insulating film. A portion of the first prefabricated insulating film is removed to expose the bumps. The bumps electrically connect the substrate to the interconnect structure.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: June 7, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: HeeJo Chi, HanGil Shin, NamJu Cho
  • Patent number: 9355939
    Abstract: A method of manufacture of an integrated circuit package system includes: providing a base package substrate including: forming component contacts on a component side of the base package substrate, forming system contacts on a system side of the base package substrate, and forming a reference voltage circuit between the component contacts and the system contacts; mounting a first integrated circuit die on the component contacts; mounting a lead frame on the first integrated circuit die and coupled to the component contacts; and isolating a conductive shield from the lead frame, the conductive shield coupled to the reference voltage circuit.
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: May 31, 2016
    Assignee: STATS ChipPAC Ltd.
    Inventors: NamJu Cho, HeeJo Chi, HanGil Shin
  • Patent number: 9312218
    Abstract: A semiconductor device has a semiconductor die mounted to a substrate. A leadframe has a base plate and integrated tie bars and conductive bodies. The tie bars include a down step with an angled surface and horizontal surface between the conductive bodies. The leadframe is mounted to the semiconductor die and substrate with the base plate disposed on a back surface of the semiconductor die and the conductive bodies disposed around the semiconductor die and electrically connected to the substrate. An encapsulant is deposited over the substrate and semiconductor die and into the down step of the tie bars. A conductive layer is formed over the conductive bodies to inhibit oxidation. The leadframe is singulated through the encapsulant in the down step and through the horizontal portion of the tie bars to electrically isolate the conductive bodies. A semiconductor package can be mounted to the substrate and semiconductor die.
    Type: Grant
    Filed: May 12, 2011
    Date of Patent: April 12, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: DaeSik Choi, SooSan Park, HanGil Shin
  • Patent number: 9299650
    Abstract: An integrated circuit packaging system and method of manufacture thereof including: a base substrate; an integrated circuit die on the base substrate; vertical interconnects attached to the base substrate around the integrated circuit die; and a single metal layer interposer mounted on the vertical interconnects, the single metal layer interposer including: a routing pattern having interposer contacts and traces, and a dielectric layer on the interposer contacts and traces, a top surface of the interposer contacts coplanar with a top surface of the dielectric layer.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: March 29, 2016
    Assignee: STATS ChipPAC Ltd.
    Inventors: HeeJo Chi, HanGil Shin, NamJu Cho, Kyung Moon Kim
  • Patent number: 9269691
    Abstract: A semiconductor device has a semiconductor die. The semiconductor die is disposed over a conductive substrate. An encapsulant is deposited over the semiconductor die. A first interconnect structure is formed over the encapsulant. An opening is formed through the substrate to isolate a portion of the substrate electrically connected to the first interconnect structure. A bump is formed over the first interconnect structure. Conductive vias are formed through the encapsulant and electrically connected to the portion of the substrate. A plurality of bumps is formed over the semiconductor die. A first conductive layer is formed over the encapsulant. A first insulating layer is formed over the first conductive layer. A second conductive layer is formed over the first insulating layer and first conductive layer. A second insulating layer is formed over the first insulating layer and second conductive layer. Protrusions extend above the substrate.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: February 23, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: HeeJo Chi, HanGil Shin, NamJu Cho