Patents by Inventor HanGil Shin

HanGil Shin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120319295
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a circuit structure having a circuit active side and a cavity from the circuit active side; mounting an integrated circuit device in the cavity; forming a base encapsulation, having a base first side facing away from the circuit active side, on the circuit active side, around the integrated circuit device, and in the cavity; forming a first conductive pin, having a first pin height, in the base encapsulation and traversing from the circuit active side to the base first side; forming a second conductive pin, having a second pin height equivalent to the first pin height, in the base encapsulation and traversing from the integrated circuit device to the base first side; and removing a portion of the circuit structure to form a circuit non-active side and expose the integrated circuit device and a base second side.
    Type: Application
    Filed: June 17, 2011
    Publication date: December 20, 2012
    Inventors: HeeJo Chi, NamJu Cho, HanGil Shin
  • Publication number: 20120306102
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base package carrier; mounting an interposer over the base package carrier; forming a base package encapsulation over the base package carrier and the interposer with the base package encapsulation having a cavity for exposing the interposer; and forming a support recess in the base package encapsulation between a non-horizontal edge of the base package encapsulation and the cavity.
    Type: Application
    Filed: May 31, 2011
    Publication date: December 6, 2012
    Inventors: NamJu Cho, HeeJo Chi, HanGil Shin
  • Patent number: 8318541
    Abstract: A semiconductor device has a plurality of semiconductor die or components mounted over a carrier. A leadframe is mounted over the carrier between the semiconductor die. The leadframe has a plate and bodies extending from the plate. The bodies of the leadframe are disposed around a perimeter of the semiconductor die. An encapsulant is deposited over the carrier, leadframe, and semiconductor die. A plurality of conductive vias is formed through the encapsulant and electrically connected to the bodies of the leadframe and contact pads on the semiconductor die. An interconnect structure is formed over the encapsulant and electrically connected to the conductive vias. A first channel is formed through the interconnect structure, encapsulant, leadframe, and partially through the carrier. The carrier is removed to singulate the semiconductor die. A second channel is formed through the plate of the leadframe to physically separate the bodies of the leadframe.
    Type: Grant
    Filed: August 10, 2010
    Date of Patent: November 27, 2012
    Assignee: STATS ChipPAC, Ltd.
    Inventors: HanGil Shin, NamJu Cho, HeeJo Chi
  • Patent number: 8318539
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a carrier having a planar surface and a cavity therein, a first barrier between the planar surface and a first interconnect, and a second barrier between the cavity and a second interconnect; providing a substrate; mounting an integrated circuit over the substrate; mounting the carrier to the substrate with the first interconnect and the second interconnect attached to the substrate and with the planar surface over the integrated circuit; forming an encapsulation between the substrate and the carrier covering the integrated circuit, the encapsulation having an encapsulation recess under the planar surface and over the integrated circuit; and removing a portion of the carrier to expose the encapsulation, a portion of the first barrier to form a first contact pad, and a portion of the second barrier to form a second contact pad.
    Type: Grant
    Filed: April 6, 2011
    Date of Patent: November 27, 2012
    Assignee: STATS ChipPAC Ltd.
    Inventors: NamJu Cho, HeeJo Chi, HanGil Shin
  • Publication number: 20120286407
    Abstract: A semiconductor device has a semiconductor die mounted to a substrate. A leadframe has a base plate and integrated tie bars and conductive bodies. The tie bars include a down step with an angled surface and horizontal surface between the conductive bodies. The leadframe is mounted to the semiconductor die and substrate with the base plate disposed on a back surface of the semiconductor die and the conductive bodies disposed around the semiconductor die and electrically connected to the substrate. An encapsulant is deposited over the substrate and semiconductor die and into the down step of the tie bars. A conductive layer is formed over the conductive bodies to inhibit oxidation. The leadframe is singulated through the encapsulant in the down step and through the horizontal portion of the tie bars to electrically isolate the conductive bodies. A semiconductor package can be mounted to the substrate and semiconductor die.
    Type: Application
    Filed: May 12, 2011
    Publication date: November 15, 2012
    Applicant: STATS CHIPPAC, LTD.
    Inventors: DaeSik Choi, SooSan Park, HanGil Shin
  • Patent number: 8288209
    Abstract: A semiconductor device has a leadframe with a plurality of bodies extending from the base plate. A first semiconductor die is mounted to the base plate of the leadframe between the bodies. An encapsulant is deposited over the first semiconductor die and base plate and around the bodies of the leadframe. A portion of the encapsulant over the bodies of the leadframe is removed to form first openings in the encapsulant that expose the bodies. An interconnect structure is formed over the encapsulant and extending into the first openings to the bodies of the leadframe. The leadframe and bodies are removed to form second openings in the encapsulant corresponding to space previously occupied by the bodies to expose the interconnect structure. A second semiconductor die is mounted over the first semiconductor die with bumps extending into the second openings of the encapsulant to electrically connect to the interconnect structure.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: October 16, 2012
    Assignee: STATS ChipPAC, Ltd.
    Inventors: HeeJo Chi, NamJu Cho, HanGil Shin
  • Publication number: 20120241925
    Abstract: A method of manufacturing of an integrated circuit packaging system includes: providing a base substrate; mounting a first die over the base substrate; mounting a second die over the first die; attaching an interposer substrate over the first die with an attachment adhesive therebetween, the interposer substrate having a central cavity and the second die within the central cavity; attaching a lateral interconnect to a second active side away from the first die of the second die and to the interposer substrate; and encapsulating the first die and the second die.
    Type: Application
    Filed: March 22, 2011
    Publication date: September 27, 2012
    Inventors: In Sang Yoon, HeeJo Chi, HanGil Shin
  • Patent number: 8264091
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting an integrated circuit over the substrate; attaching a buffer interconnect to and over the substrate; forming an encapsulation over the substrate covering the buffer interconnect and the integrated circuit; and forming a via in the encapsulation and to the buffer interconnect.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: September 11, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: NamJu Cho, HeeJo Chi, HanGil Shin
  • Patent number: 8247894
    Abstract: An integrated circuit package system includes: providing a stackable integrated circuit package system having a base encapsulation and a recess therein; stacking a top integrated circuit package system, having a top encapsulation with a protruding portion, with the stackable integrated circuit package system with the protruding portion aligned and matched within the recess; and connecting the top integrated circuit package system and the stackable integrated circuit package system.
    Type: Grant
    Filed: March 24, 2008
    Date of Patent: August 21, 2012
    Assignee: STATS ChipPAC Ltd.
    Inventors: In Sang Yoon, HanGil Shin, Jae Han Chung, DeokKyung Yang
  • Publication number: 20120168916
    Abstract: A semiconductor device is made by mounting a semiconductor wafer to a temporary carrier. A plurality of TSV is formed through the wafer. A cavity is formed partially through the wafer. A first semiconductor die is mounted to a second semiconductor die. The first and second die are mounted to the wafer such that the first die is disposed over the wafer and electrically connected to the TSV and the second die is disposed within the cavity. An encapsulant is deposited over the wafer and first and second die. A portion of the encapsulant is removed to expose a first surface of the first die. A portion of the wafer is removed to expose the TSV and a surface of the second die. The remaining portion of the wafer operates as a TSV interposer for the first and second die. An interconnect structure is formed over the TSV interposer.
    Type: Application
    Filed: March 14, 2012
    Publication date: July 5, 2012
    Applicant: STATS CHIPPAC, LTD.
    Inventors: HeeJo Chi, NamJu Cho, HanGil Shin
  • Publication number: 20120153467
    Abstract: A semiconductor wafer has a plurality of first semiconductor die. A second semiconductor die is mounted to the first semiconductor die. The active surface of the first semiconductor die is oriented toward an active surface of the second semiconductor die. An encapsulant is deposited over the first and second semiconductor die. A portion of a back surface of the second semiconductor die opposite the active surface is removed. Conductive pillars are formed around the second semiconductor die. TSVs can be formed through the first semiconductor die. An interconnect structure is formed over the back surface of the second semiconductor die, encapsulant, and conductive pillars. The interconnect structure is electrically connected to the conductive pillars. A portion of a back surface of the first semiconductor die opposite the active surface is removed. A heat sink or shielding layer can be formed over the back surface of the first semiconductor die.
    Type: Application
    Filed: February 23, 2012
    Publication date: June 21, 2012
    Applicant: STATS CHIPPAC, LTD.
    Inventors: HeeJo Chi, NamJu Cho, HanGil Shin
  • Publication number: 20120153505
    Abstract: A semiconductor wafer has a plurality of first semiconductor die. A second semiconductor die is mounted to the first semiconductor die. The active surface of the first semiconductor die is oriented toward an active surface of the second semiconductor die. An encapsulant is deposited over the first and second semiconductor die. A portion of a back surface of the second semiconductor die opposite the active surface is removed. Conductive pillars are formed around the second semiconductor die. TSVs can be formed through the first semiconductor die. An interconnect structure is formed over the back surface of the second semiconductor die, encapsulant, and conductive pillars. The interconnect structure is electrically connected to the conductive pillars. A portion of a back surface of the first semiconductor die opposite the active surface is removed. A heat sink or shielding layer can be formed over the back surface of the first semiconductor die.
    Type: Application
    Filed: February 23, 2012
    Publication date: June 21, 2012
    Applicant: STATS CHIPPAC, LTD.
    Inventors: HeeJo Chi, NamJu Cho, HanGil Shin
  • Patent number: 8202797
    Abstract: A method of manufacture of an integrated circuit system includes: providing a substrate with a face surface having a via therein and a back surface having a trench therein; filling the via with a conductive pillar; forming a recessed contact pad in the trench; filling the recessed contact pad partially with solder; and forming an under-bump metal having a base surface in electrical contact with the conductive pillar, and having sides that extend away from the face surface of the substrate and further extend beyond the base surface.
    Type: Grant
    Filed: June 22, 2010
    Date of Patent: June 19, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: HeeJo Chi, NamJu Cho, HanGil Shin
  • Publication number: 20120119393
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a package substrate having a foldable segment, a base segment, and a stack segment; connecting a base substrate connector directly on the base segment; connecting a stack substrate connector directly on the stack segment; mounting a base integrated circuit over the base segment with the base substrate connector outside a perimeter of the base integrated circuit; and folding the package substrate with the stack segment over the base segment and the stack substrate connector directly on the base substrate connector.
    Type: Application
    Filed: November 17, 2010
    Publication date: May 17, 2012
    Inventors: HeeJo Chi, NamJu Cho, HanGil Shin
  • Publication number: 20120119388
    Abstract: A semiconductor device has an interposer frame mounted over a carrier. A semiconductor die has an active surface and bumps formed over the active surface. The semiconductor die can be mounted within a die opening of the interposer frame or over the interposer frame. Stacked semiconductor die can also be mounted within the die opening of the interposer frame or over the interposer frame. Bond wires or bumps are formed between the semiconductor die and interposer frame. An encapsulant is deposited over the interposer frame and semiconductor die. An interconnect structure is formed over the encapsulant and bumps of the first semiconductor die. An electronic component, such as a discrete passive device, semiconductor die, or stacked semiconductor die, is mounted over the semiconductor die and interposer frame. The electronic component has an I/O count less than an I/O count of the semiconductor die.
    Type: Application
    Filed: November 16, 2010
    Publication date: May 17, 2012
    Applicant: STATS CHIPPAC, LTD.
    Inventors: NamJu Cho, HeeJo Chi, HanGil Shin
  • Publication number: 20120086115
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit; mounting a routing structure having a functional side above the integrated circuit; mounting a vertical interconnect to the functional side of the routing structure and the vertical interconnect extending vertically away from the routing structure; forming an encapsulation covering the integrated circuit, the routing structure, and sides of the vertical interconnect above the routing structure, and leaves a surface of the routing structure exposed from the encapsulation, and a portion of the vertical interconnect exposed from the encapsulation above the surface of the routing structure; mounting a first-external-package-component to the routing structure; and forming a first-external-package-encapsulation covering the first-external-package-component.
    Type: Application
    Filed: December 13, 2011
    Publication date: April 12, 2012
    Inventors: A Leam Choi, Kenny Lee, In Sang Yoon, HanGil Shin
  • Patent number: 8143097
    Abstract: A semiconductor device is made by mounting a semiconductor wafer to a temporary carrier. A plurality of TSV is formed through the wafer. A cavity is formed partially through the wafer. A first semiconductor die is mounted to a second semiconductor die. The first and second die are mounted to the wafer such that the first die is disposed over the wafer and electrically connected to the TSV and the second die is disposed within the cavity. An encapsulant is deposited over the wafer and first and second die. A portion of the encapsulant is removed to expose a first surface of the first die. A portion of the wafer is removed to expose the TSV and a surface of the second die. The remaining portion of the wafer operates as a TSV interposer for the first and second die. An interconnect structure is formed over the TSV interposer.
    Type: Grant
    Filed: September 23, 2009
    Date of Patent: March 27, 2012
    Assignee: STATS ChipPAC, Ltd.
    Inventors: HeeJo Chi, NamJu Cho, HanGil Shin
  • Publication number: 20120068332
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a stack substrate with a component side; connecting an integrated circuit component to the component side; attaching a conductive post to the component side and adjacent the integrated circuit component, the conductive post having a protruded end above the integrated circuit component; forming a protection layer on a top and sides of the protruded end, the protection layer having a width equal to a width of the conductive post; applying a stack encapsulation over the integrated circuit component, over the stack substrate, and around a portion of the conductive post, the protection layer exposed from the stack encapsulation; and mounting a base package under the stack substrate, base package connected to the stack substrate.
    Type: Application
    Filed: September 17, 2010
    Publication date: March 22, 2012
    Inventors: DongSam Park, HanGil Shin, HeeJo Chi
  • Patent number: 8138014
    Abstract: A semiconductor wafer has a plurality of first semiconductor die. A second semiconductor die is mounted to the first semiconductor die. The active surface of the first semiconductor die is oriented toward an active surface of the second semiconductor die. An encapsulant is deposited over the first and second semiconductor die. A portion of a back surface of the second semiconductor die opposite the active surface is removed. Conductive pillars are formed around the second semiconductor die. TSVs can be formed through the first semiconductor die. An interconnect structure is formed over the back surface of the second semiconductor die, encapsulant, and conductive pillars. The interconnect structure is electrically connected to the conductive pillars. A portion of a back surface of the first semiconductor die opposite the active surface is removed. A heat sink or shielding layer can be formed over the back surface of the first semiconductor die.
    Type: Grant
    Filed: January 29, 2010
    Date of Patent: March 20, 2012
    Assignee: STATS ChipPAC, Ltd.
    Inventors: HeeJo Chi, NamJu Cho, HanGil Shin
  • Publication number: 20120038034
    Abstract: A semiconductor device has a plurality of semiconductor die or components mounted over a carrier. A leadframe is mounted over the carrier between the semiconductor die. The leadframe has a plate and bodies extending from the plate. The bodies of the leadframe are disposed around a perimeter of the semiconductor die. An encapsulant is deposited over the carrier, leadframe, and semiconductor die. A plurality of conductive vias is formed through the encapsulant and electrically connected to the bodies of the leadframe and contact pads on the semiconductor die. An interconnect structure is formed over the encapsulant and electrically connected to the conductive vias. A first channel is formed through the interconnect structure, encapsulant, leadframe, and partially through the carrier. The carrier is removed to singulate the semiconductor die. A second channel is formed through the plate of the leadframe to physically separate the bodies of the leadframe.
    Type: Application
    Filed: August 10, 2010
    Publication date: February 16, 2012
    Applicant: STATS CHIPPAC, LTD.
    Inventors: HanGil Shin, NamJu Cho, HeeJo Chi