Patents by Inventor Hann Wang

Hann Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250006196
    Abstract: Techniques for generating a prompt for a language model to determine an action responsive to a user input, are described. In some embodiments, the system receives a user input, determines one or more application programming interfaces (APIs) configured to perform actions that are relevant to the user input and exemplars representing examples of using the APIs with respect to user inputs similar to the current user input. The system further determines device states of devices that are determined to be related to the user input and also determines other contextual information (e.g., weather information, time of day, geographic location, etc.). The system generates a prompt including the user input, the APIs, the exemplars, the device states, and the other contextual information. A language model processes the prompt to determine an action responsive to the user input and the system causes performance of the action.
    Type: Application
    Filed: June 30, 2023
    Publication date: January 2, 2025
    Inventors: Hann Wang, Angeliki Metallinou, Melanie C B Gens, Arijit Biswas, Ying Shi
  • Publication number: 20230204508
    Abstract: A detection method and a detection system for detecting objects of interest attached to a surface of a plurality of reporters, wherein the plurality of reporters are flowing in a microfluidic chip and illuminated by a light source. The detection method has following steps: obtaining a plurality of local surface plasmon resonance (LSPR) spectral images of each the plurality of the reporters individually, wherein each of the LSPR spectral images has a brightness of a long wavelength band (BA) and a brightness of a short wavelength band (BB); calculating a spectral image brightness contrast ? for each of the LSPR spectral images, wherein ? = B A - B B B A + B B ; and, defining a positive threshold for |?|?0.1.
    Type: Application
    Filed: December 20, 2022
    Publication date: June 29, 2023
    Inventors: Pei-Kuen WEI, Sheng-Hann WANG, Ting-Wei CHANG
  • Publication number: 20180128726
    Abstract: According to an embodiment of the present disclosure, an analysis apparatus may include a movable carrier, a sample providing device and a first analysis device. The movable carrier has at least one sample carry region, and moves the sample carry region to at least one collection position and an analysis position. The sample providing device provides a plurality of samples, wherein the sample carry region receives a portion of the samples at the collection position. The first analysis device may be aligned to the analysis position, and analyzes the samples on the sample carry region located at the analysis position.
    Type: Application
    Filed: December 29, 2016
    Publication date: May 10, 2018
    Applicant: Industrial Technology Research Institute
    Inventors: Yen-Liang Lin, Sheng-Hann Wang, Yu-Shan Yeh, Hsin-Chia Ho, Wei-En Fu
  • Publication number: 20170177834
    Abstract: A cost function is specified to optimize a combination of N drugs, where the cost function includes at least one phenotypic contribution corresponding to efficacy and at least one phenotypic contribution corresponding to safety, and at least one of the N drugs is a nanomaterial-modified drug, with N being 2 or more. In vitro or in vivo tests are conducted by applying varying combinations of dosages of the N drugs to determine the phenotypic contributions from results of the tests. The results of the tests are fitted into a representation of the cost function, and, using the representation of the cost function, at least one optimized combination of dosages of the N drugs is identified.
    Type: Application
    Filed: March 23, 2015
    Publication date: June 22, 2017
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Chih-Ming HO, Dean HO, Hann WANG, Dong-Keun LEE, Kai-Yu CHEN
  • Publication number: 20160246919
    Abstract: A system includes a drug database, a disease gene database, and a network model describing a physiological or biological network. The network model receives drug data from the drug database related to drugs used in an experiment, and receives disease gene data from the disease gene database related to subjects analyzed in the experiment. The network model identifies propagation of drugs and disease through the physiological or biological network from the drug data and the disease gene data, and outputs a set of system response predictors based on the identification of the propagation. The system further includes a predictive module that receives the system response predictors, receives result data related to outcomes of the experiment, and generates a system response model based on the system response predictors and the result data.
    Type: Application
    Filed: October 7, 2014
    Publication date: August 25, 2016
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventor: Hann Wang
  • Patent number: 8745306
    Abstract: A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: June 3, 2014
    Assignee: Intel Corporation
    Inventors: Linda J. Rankin, Paul R. Pierce, Gregory E. Dermer, Wen-Hann Wang, Kai Cheng, Richard H. Hofsheier, Nitin Y. Borkar
  • Publication number: 20120317328
    Abstract: A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.
    Type: Application
    Filed: August 21, 2012
    Publication date: December 13, 2012
    Inventors: Linda J. Rankin, Paul R. Pierce, Gregory E. Dermer, Wen-Hann Wang, Kai Cheng, Richard H. Hofsheier, Nitin Y. Borkar
  • Patent number: 8255605
    Abstract: A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BICS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.
    Type: Grant
    Filed: March 30, 2011
    Date of Patent: August 28, 2012
    Assignee: Intel Corporation
    Inventors: Linda J. Rankin, Paul R. Pierce, Gregory E. Dermer, Wen-Hann Wang, Kai Cheng, Richard H Hofsheier, Nitin Y. Borkar
  • Publication number: 20110185101
    Abstract: A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.
    Type: Application
    Filed: March 30, 2011
    Publication date: July 28, 2011
    Inventors: Linda J. Rankin, Paul R. Pierce, Gregory E. Dermer, Wen-Hann Wang, Kai Cheng, Richard H. Hofsheier, Nitin Y. Borkar
  • Patent number: 7930464
    Abstract: A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.
    Type: Grant
    Filed: August 28, 2009
    Date of Patent: April 19, 2011
    Assignee: Intel Corporation
    Inventors: Linda J. Rankin, Paul R. Pierce, Gregory E. Dermer, Wen-Hann Wang, Kai Cheng, Richard H. Hofsheier, Nitin Y. Borkar
  • Patent number: 7670550
    Abstract: A method of sterilizing an article includes placing the article into a chamber containing an inner atmosphere and exhausting the inner atmosphere to lower pressure in the chamber. Hydrogen peroxide vapor is present in the chamber during at least a portion of the step of exhausting the inner atmosphere. Exhaustion of the inner atmosphere is terminated and additional hydrogen peroxide is admitted into the chamber. Hydrogen peroxide vapor contacts the article for a sufficient period to effect sterilization of the article.
    Type: Grant
    Filed: March 30, 2005
    Date of Patent: March 2, 2010
    Assignee: Ethicon, Inc.
    Inventors: Szu-Min Lin, Paul T. Jacobs, Jenn-Hann Wang, James P. Kohler, Richard Jed Kendall, Harold R. Williams, Robert Lukasik
  • Publication number: 20090319717
    Abstract: A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.
    Type: Application
    Filed: August 28, 2009
    Publication date: December 24, 2009
    Inventors: Linda J. Rankin, Paul R. Pierce, Gregory E. Dermer, Wen-Hann Wang, Kai Cheng, Richard H. Hofsheier, Nitin Y. Borkar
  • Patent number: 7603508
    Abstract: A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.
    Type: Grant
    Filed: January 14, 2008
    Date of Patent: October 13, 2009
    Assignee: Intel Corporation
    Inventors: Linda J. Rankin, Paul R. Pierce, Gregory E. Dermer, Wen-Hann Wang, Kai Cheng, Richard H. Hofsheier, Nitin Y. Borkar
  • Patent number: 7563329
    Abstract: A method for monitoring a cleaning process for a medical instrument, includes the steps of placing the instrument in a cleaning chamber; placing a soil standard in the cleaning chamber; cleaning the instrument and the soil standard with a cleaning solution; and detecting whether soil remains on said soil standard. The soil standard includes two substantially parallel substrates separated with two substantially equal thickness spacers, wherein a gap is formed between the two substrates with soil in the gap.
    Type: Grant
    Filed: March 31, 2005
    Date of Patent: July 21, 2009
    Assignee: Ethicon Inc.
    Inventors: Szu-Min Lin, Paul T. Jacobs, Jenn-Hann Wang, Robert C. Platt, Peter C. Zhu
  • Publication number: 20090149728
    Abstract: The invention provides methods and apparatus for detecting an analyte in blood. The apparatus is particularly suited for bringing a sensor into direct contact with blood in vivo. The apparatus comprises a sensor that detects the presence of an analyte and an assembly means. The assembly means has a sensor end, wherein the sensor end of the assembly means is affixed to the sensor, and the assembly means is adapted for coupling with a venous flow device. By coupling with a venous flow device, the assembly means brings the sensor into direct contact with blood flowing through the venous flow device. Examples of venous flow devices that bring the sensor into direct contact with the blood of a subject include, but are not limited to, intravenous catheters and external blood loops, such as are used in extra corporeal membrane oxygenation or hemodialysis.
    Type: Application
    Filed: November 4, 2008
    Publication date: June 11, 2009
    Applicant: MEDTRONIC MINIMED, INC.
    Inventors: Nannette M. Van Antwerp, Bradley J. Enegren, John J. Mastrototaro, Rajiv Shah, Udo Hoss, Yanan Zhang, Jenn-Hann Wang, Kent L. Clark
  • Patent number: 7468033
    Abstract: The invention provides methods and apparatus for detecting an analyte in blood. The apparatus is particularly suited for bringing a sensor into direct contact with blood in vivo. The apparatus comprises a sensor that detects the presence of an analyte and an assembly means. The assembly means has a sensor end, wherein the sensor end of the assembly means is affixed to the sensor, and the assembly means is adapted for coupling with a venous flow device. By coupling with a venous flow device, the assembly means brings the sensor into direct contact with blood flowing through the venous flow device. Examples of venous flow devices that bring the sensor into direct contact with the blood of a subject include, but are not limited to, intravenous catheters and external blood loops, such as are used in extra corporeal membrane oxygenation or hemodialysis.
    Type: Grant
    Filed: September 8, 2004
    Date of Patent: December 23, 2008
    Assignee: Medtronic MiniMed, Inc.
    Inventors: Nannette M. Van Antwerp, Bradley J. Enegren, John J. Mastrototaro, Rajiv Shah, Udo Hoss, Yanan Zhang, Jenn-Hann Wang, Kent L. Clark
  • Publication number: 20080114919
    Abstract: A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.
    Type: Application
    Filed: January 14, 2008
    Publication date: May 15, 2008
    Inventors: Linda Rankin, Paul Pierce, Gregory Dermer, Wen-Hann Wang, Kai Cheng, Richard Hofsheier, Nitin Borkar
  • Patent number: 7343442
    Abstract: A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.
    Type: Grant
    Filed: June 6, 2006
    Date of Patent: March 11, 2008
    Assignee: Intel Corporation
    Inventors: Linda J. Rankin, Paul R. Pierce, Gregory E. Dermer, Wen-Hann Wang, Kai Cheng, Richard H. Hofsheier, Nitin Y. Borkar
  • Patent number: 7252800
    Abstract: A chemical vapor sterilization process is enhanced by concentrating a germicide via exploitation of the difference between the vapor pressures of the germicide and its solvent. A diffusion restriction can be placed into the diffusion path to assist this process and the path then opened to provide rapid diffusion of the thus concentrated germicide.
    Type: Grant
    Filed: March 31, 2003
    Date of Patent: August 7, 2007
    Assignee: Ethicon, Inc.
    Inventors: Paul T. Jacobs, Szu-Min Lin, Jenn-Hann Wang, James P. Kohler, Richard Jed Kendall, Anahid Gamsarian
  • Patent number: 7246627
    Abstract: An apparatus for monitoring a cleaning process for a medical device includes a cleaning chamber for receiving and cleaning the instrument with a cleaning liquid, a receiving well within the cleaning chamber, a removable soil standard receivable within the receiving well whereby to be exposed to the cleaning process within the cleaning chamber; and a soil detector coupled to the cleaning chamber and adapted to provide an indication of the amount of the soil on the soil standard while the soil standard is received within the receiving well.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: July 24, 2007
    Assignee: Ethicon, Inc.
    Inventors: Paul T. Jacobs, Jenn-Hann Wang, Szu-Min Lin