Abstract: According to the invention, hardware assisted dynamic optimization of program execution is disclosed. According to one embodiment, an application process executed by a microprocessor is optimized by selecting one or more microarchitecture events relating to the execution of the application process to be monitored by one or more hardware monitors; establishing parameters regarding the monitoring of the microarchitecture events by setting one or more monitor control vectors; processing profile data captured by the hardware monitors regarding the occurrence of the microarchitecture events; identifying a region of interest in the application process for optimization based at least in part on the captured profile data; and optimizing the region of interest in the application process.

Abstract: According to the invention, an apparatus and method are disclosed for configurable system monitoring for dynamic optimization of program execution. According to one embodiment, an event monitoring apparatus for dynamic optimization comprises an event monitor to capture profiles of events that occur in the processing of an application by a microprocessor; an interface to a software component; monitor control vectors to direct the operation of the event monitor; and a profile buffer. According to the embodiment, the events to be monitored are selected by the software component. Profiles of the selected events are captured and stored in the profile buffer. The profiles are made available to a handler routine selected by the software component, which processes the profiles to identify regions of the application for optimization and invokes optimizers to optimize the identified regions.

Abstract: A device, and its production method, the device has a substrate and a coating composition, the coating composition being formed by the gas phase or plasma polymerization of a gas comprising at least one organic compound or monomer. The polymerization is carried out using a pulsed discharge having a duty cycle of less than about ⅕, in which the pulse-on time is less than about 100 msec and the pulse-off time is less than about 2000 msec. The duty cycle can also be varied, thus the coating composition can be gradient layered accordingly. The device has a coating composition which is uniform in thickness, pin-hole free, optically transparent in the visible region of the magnetic spectrum, permeable to oxygen, abrasive resistant, wettable and biologically non-fouling.

Abstract: A method for sterilizing the interior of a diffusion restricted area by introducing a sterilant in a chamber, condensing the vapor, reducing the pressure in the chamber to revaporize the condensed vapor, and maintaining the device in the chamber until the device is sterilized. The sterilant has a vapor pressure less than the vapor pressure of water and is preferably hydrogen peroxide. The pressure in the chamber while maintaining the device in the chamber may be held constant, varied, or increased. Plasma may additionally be introduced into the chamber to improve the rate of sterilization.

Abstract: A method for sterilizing a device, includes the following steps: contacting the device with liquid sterilant outside or inside a sterilization chamber at a first pressure, placing the device in the chamber before or after the contacting step, and decreasing the pressure of the chamber to a second pressure below the vapor pressure of the liquid sterilant. At least the decrease in pressure below about the vapor pressure of the liquid sterilant occurs at a pumpdown rate of less than 0.8 liters per second, calculated based on the time required to evacuate the chamber from atmospheric pressure to 20 torr when the chamber is empty and dry.

Abstract: The present invention discloses a method for microelectrogravimetrically depositing an electroactive species onto an electrode or a plurality of electrodes. The method comprises dispensing a solution containing the electroactive species from a microdispenser so as to form a hanging drop of the solution. The method further comprises contacting the electrode with the hanging drop of the solution, wherein the electrode is electrically coupled with the microdispenser so as to form an electrochemical cell, and applying a potential to the electrochemical cell. The application of the potential effects deposition of the electroactive species onto the electrode. The method of the invention eliminates the need for immersion of the electrode in a bath, reduces the volume of solution required by a factor of at least 10-100, and avoids uneven depletion of various components of the solution over successive applications.

Abstract: A method for determining and sterilizing a load in a sterilization chamber. A small amount of sterilant is introduced into the sterilization chamber and the concentration of sterilant is measured. The load of equipment to be sterilized is determined from the concentration of sterilant, and more sterilant is added, if necessary, based on the load. The process is repeated, if necessary, until the load is sterilized. The sterilant is preferably hydrogen peroxide, and the concentration of hydrogen peroxide is preferably determined by a spectrophotometric method in the infrared or ultraviolet regions. By monitoring the sterilant concentration and adding more as needed, the equipment in the chamber can be sterilized efficiently without exposing it to high concentrations of sterilant which could damage the equipment or leave too much residual on the equipment.

Abstract: Disclosed is a method for microelectrogravimetrically depositing an electroactive species onto an electrode or a plurality of electrodes comprising dispensing a solution containing the electroactive species from a microdispenser to form a hanging drop of the solution and contacting the electrode with the hanging drop of the solution, wherein the electrode is electrically coupled with the microdispenser to form an electrochemical cell, and applying a potential to the electrochemical cell. The application of the potential effects deposition of the electroactive species onto the electrode. The method of the invention eliminates the need for immersion of the electrode in a bath, reduces the volume of solution required by a factor of at least 10-100, and avoids uneven depletion of various components of the solution over successive applications.

Abstract: A method for determining and sterilizing a load in a sterilization chamber. A small amount of sterilant is introduced into the sterilization chamber and the concentration of sterilant is measured. The load of equipment to be sterilized is determined from the concentration of sterilant, and more sterilant is added, if necessary, based on the load. The process is repeated, if necessary, until the load is sterilized. The sterilant is preferably hydrogen peroxide, and the concentration of hydrogen peroxide is preferably determined by a spectrophotometric method in the infrared or ultraviolet regions. By monitoring the sterilant concentration and adding more as needed, the equipment in the chamber can be sterilized efficiently without exposing it to high concentrations of sterilant which could damage the equipment or leave too much residual on the equipment.

Abstract: A method for sterilizing a device, includes the following steps: contacting the device with liquid sterilant outside or inside a sterilization chamber at a first pressure, placing the device in the chamber before or after the contacting step, and decreasing the pressure of the chamber to a second pressure below the vapor pressure of the liquid sterilant. At least the decrease in pressure below about the vapor pressure of the liquid sterilant occurs at a pumpdown rate of less than 0.8 liters per second, calculated based on the time required to evacuate the chamber from atmospheric pressure to 20 torr when the chamber is empty and dry.

Abstract: This invention describes a new approach to three-dimensional molecular tailoring of surfaces. In this process, a plasma deposition step is initially employed to deposit reactive functional groups on the surface of a solid substrate. This is then followed by immersion of the coated substrate in a solution during which time solute molecules react with the functional surface groups introduced during the plasma process. Solute molecules are attached to the surface during this second step. This simple two-step process is of general utility in that both the nature of the plasma introduced surface group and the nature of the solute molecules can be varied. Additionally it is possible to provide exact control of the surface density of reactive groups introduced during the plasma process and thus the concentration of solute molecules coupled to the solid surfaces.

Abstract: In a computer system, an apparatus for handling lock conditions wherein a first instruction executed by a first processor processes data that is common to a second processor while the second processor is locked from simultaneously executing a second instruction that also processes this same data. A lock bit is set when the first processor begins execution of the first instruction. Thereupon, the second processor is prevented from executing its instruction until the first processor has completed its processing of the shared data. Hence, the second processor queues its request in a buffer. The lock bit is cleared after the first processor has completed execution of its instruction. The first processor then checks the buffer for any outstanding requests. In response to the second processor's queued request, the first processor transmits a signal to the second processor indicating that the data is now not locked.

Abstract: The present invention includes a computer system having an on-processor predictor tag array, an off-processor cache memory, and comparison circuitry. The on-processor predictor tag array contains first portions of tag information for multiple ways and multiple sets. The off-processor cache memory includes memory locations to store data and second portions of tag information. The comparison circuitry makes a first comparison of a first portion of an address with the first portions of tag information for the ways of one of the sets and uses results of the first comparison in predicting which of the ways, if any, correspond to the address. The comparison circuitry also makes a second comparison of the second portion of the address with sections of the second portions of tag information identified by the predicted way and the address.

Abstract: This invention describes a new approach to three-dimensional molecular tailoring of surfaces. In this process, a plasma deposition step is initially employed to deposit reactive functional groups on the surface of a solid substrate. This is then followed by immersion of the coated substrate in a solution during which time solute molecules react with the functional surface groups introduced during the plasma process. Solute molecules are attached to the surface during this second step. This simple two-step process is of general utility in that both the nature of the plasma introduced surface group and the nature of the solute molecules can be varied. Additionally it is possible to provide exact control of the surface density of reactive groups introduced during the plasma process and thus the concentration of solute molecules coupled to the solid surfaces.

Abstract: A system and method for reducing the number of writeback operations performed by level two (L2) or higher level cache memories in a microprocessor system having an integrated hierarchical cache structure. Writeback operations of modified victim lines in L2 or higher level caches are cancelled if an associated cache line, having a "modified" status, is located in a lower level cache. In one embodiment of the present invention, writeback operations of modified victim lines in L2 or higher level caches are also cancelled if an associated cache line, having a "clean" status, is located in a lower level cache.

Abstract: A method and apparatus for cache memory replacement line identification have a cache interface which provides a communication interface between a cache memory and a controller for the cache memory. The interface includes an address bus, a data bus, and a status bus. The address bus transfers requested addresses from the controller to the cache memory. The data bus transfers data associated with requested addresses from the controller to the cache memory, and also transfers replacement line addresses from the cache memory to the controller. The status bus transfers status information associated with the requested addresses from the cache memory to the controller which indicate whether the requested addresses are contained in the cache memory. In one embodiment, the data bus also transfers cache line data associated with a requested address from the cache memory to the controller when the requested address hits the cache memory.

Abstract: A computer system comprising a plurality of caching agents with a cache hierarchy, the caching agents sharing memory across a system bus and issuing memory access requests in accordance with a protocol wherein a line of a cache has a present state comprising one of a plurality of line states. The plurality of line states includes a modified (M) state, wherein a line of a first caching agent in M state has data which is more recent than any other copy in the system; an exclusive (E) state, wherein a line in E state in a first caching agent is the only one of the agents in the system which has a copy of the data in a line of the cache, the first caching agent modifying the data in the cache line independent of other said agents coupled to the system bus; a shared (S) state, wherein a line in S state indicates that more than one of the agents has a copy of the data in the line; and an invalid (I) state indicating that the line does not exist in the cache.

Abstract: A method and apparatus for transferring information between a processor and a memory system utilizing a chunk write buffer, where read and write requests to the L2 cache memory are controlled by the processor. The cache line associated with each such request is larger than the interface coupling the L2 cache memory and the processor. Read requests are returned from the L2 cache memory to the processor in burst fashion. Write requests are transferred from the processor to the L2 cache memory during clock cycles in which the processor does not require the interface for a read request. Write requests need not be transferred in burst fashion; rather, a portion of the write request corresponding to the size of the interface, referred to as a chunk, is transferred from the processor to the L2 cache memory and stored temporarily in the chunk write buffer.

Abstract: A cache memory with reduced request-blocking blocks requests from being accepted by the cache memory based on the types of requests the cache is already servicing. A request which hits the cache memory or a request which misses the cache memory but does not conflict with any requests already being serviced is not blocked. A request which misses the cache memory and also conflicts with a request(s) already being serviced causes the request to be blocked. In one embodiment, conflicts for write requests are determined by checking whether the cache is already retrieving a cache line from system memory for a request which maps into the same cache set as the write request. If such a request exists, then a conflict occurs. In this embodiment, conflicts for read requests are determined by checking whether the cache is already servicing an outstanding request to memory for the same address. If so, then a conflict occurs.

Abstract: A protection update buffer in conjunction with a cache memory that stores data, protection information and data line tags. The protection update buffer also stores cache address tags. By storing cache tags in the protection update buffer, the protection update buffer may alert the cache memory of lines that have had protection bits change. Also, by further storing data protection information in the protection update buffer, it is possible for the protection update buffer to provide correct protection information for cached data. If writing a tag and/or data protection information to the protection update buffer causes an overflow of the protection update buffer, then the associated cache is flushed and the entries of the protection update buffer are cleared.