Patents by Inventor Hans-Joachim Schulze

Hans-Joachim Schulze has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11081393
    Abstract: A method of splitting a semiconductor wafer includes: forming one or more epitaxial layers on the semiconductor wafer; forming a plurality of device structures in the one or more epitaxial layers; forming a metallization layer and/or a passivation layer over the plurality of device structures; attaching a carrier to the semiconductor wafer with the one or more epitaxial layers, the carrier protecting the plurality of device structures and mechanically stabilizing the semiconductor wafer; forming a separation region within the semiconductor wafer, the separation region having at least one altered physical property which increases thermo-mechanical stress within the separation region relative to the remainder of the semiconductor wafer; and applying an external force to the semiconductor wafer such that at least one crack propagates along the separation region and the semiconductor wafer splits into two separate pieces, one of the pieces retaining the plurality of device structures.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: August 3, 2021
    Assignee: Infineon Technologies AG
    Inventors: Christian Beyer, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze, Marko Swoboda
  • Patent number: 11081544
    Abstract: A method of manufacturing a device in a semiconductor body includes forming a first field stop zone portion of a first conductivity type and a drift zone of the first conductivity type on the first field stop zone portion. An average doping concentration of the drift zone is smaller than 80% of that of the first field stop zone portion. The semiconductor body is processed at a first surface and thinned by removing material from a second surface. A second field stop zone portion of the first conductivity type is formed by implanting protons at one or more energies through the second surface. A deepest end-of-range peak of the protons is set in the first field stop zone portion at a vertical distance to a transition between the drift zone and first field stop zone portion in a range from 3 ?m to 60 ?m. The semiconductor body is annealed.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: August 3, 2021
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Franz-Josef Niedernostheide, Oana Julia Spulber, Stephan Voss
  • Publication number: 20210225798
    Abstract: A method for fabricating a semiconductor die package includes: providing a semiconductor transistor die, the semiconductor transistor die having a first contact pad on a first lower main face and/or a second contact pad on an upper main face; fabricating a frontside electrical conductor onto the second contact pad and a backside electrical conductor onto the first contact pad; and applying an encapsulant covering the semiconductor die and at least a portion of the electrical conductor, wherein the frontside electrical conductor and/or the backside electrical conductor is fabricated by laser-assisted structuring of a metallic structure.
    Type: Application
    Filed: January 15, 2021
    Publication date: July 22, 2021
    Inventors: Edward Fuergut, Irmgard Escher-Poeppel, Martin Gruber, Ivan Nikitin, Hans-Joachim Schulze
  • Patent number: 11069626
    Abstract: A molding compound and a semiconductor arrangement with a molding compound are disclosed. The molding compound includes a matrix and a filler including filler particles. The filler particles each include a core with an electrically conducting or a semiconducting material and an electrically insulating cover.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: July 20, 2021
    Assignee: Infineon Technologies AG
    Inventors: Anton Mauder, Oliver Hellmund, Peter Irsigler, Hanno Melzner, Stefan Miethaner, Sebastian Schmidt, Hans-Joachim Schulze
  • Patent number: 11063142
    Abstract: A semiconductor device includes a silicon carbide body that includes a first section and a second section. The first section is adjacent to the second section. A drift region is formed in the first section and the second section. A lattice defect region is in a portion of the drift region in the second section. A first density of lattice defects, which include interstitials and vacancies in the lattice defect region, is at least double a second density of lattice defects, which include interstitials and vacancies in a portion of the drift region outside the lattice defect region.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: July 13, 2021
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Jens Peter Konrath, Wolfgang Bergner, Christian Hecht, Hans-Joachim Schulze, Andre Rainer Stegner
  • Publication number: 20210193435
    Abstract: In an example, a substrate is oriented to a target axis, wherein a residual angular misalignment between the target axis and a preselected crystal channel direction in the substrate is within an angular tolerance interval. Dopant ions are implanted into the substrate using an ion beam that propagates along an ion beam axis. The dopant ions are implanted at implant angles between the ion beam axis and the target axis. The implant angles are within an implant angle range. A channel acceptance width is effective for the preselected crystal channel direction. The implant angle range is greater than 80% of a sum of the channel acceptance width and twofold the angular tolerance interval. The implant angle range is smaller than 500% of the sum of the channel acceptance width and twofold the angular tolerance interval.
    Type: Application
    Filed: December 18, 2020
    Publication date: June 24, 2021
    Inventors: Moriz JELINEK, Michael HELL, Caspar LEENDERTZ, Kristijan Luka MLETSCHNIG, Hans-Joachim SCHULZE
  • Publication number: 20210193800
    Abstract: A power semiconductor device includes: a semiconductor body; a first load terminal structure coupled to the body front side and a second load terminal structure coupled to the body backside; an active area for conducting a load current between the load terminal structures; a drift region having a first conductivity type; a backside region arranged at the backside and including, inside the active area, first and second backside emitter zones. At least one of the backside emitter zones includes: first sectors each having at least one first region of a second conductivity type, the first region arranged in contact with the second load terminal structure and having a smallest lateral extension of at most 50 ?m; and/or second sectors each having a second region of the second conductivity type arranged in contact with the second load terminal structure and having a smallest lateral extension of at least 50 ?m.
    Type: Application
    Filed: December 11, 2020
    Publication date: June 24, 2021
    Inventors: Roman Baburske, Moritz Hauf, Hans-Joachim Schulze, Holger Schulze, Benedikt Stoib
  • Patent number: 11043384
    Abstract: A method of manufacturing a semiconductor device includes reducing a thickness of a semiconductor substrate and/or forming a doped region in the semiconductor substrate. The method further includes changing an ion acceleration energy of an ion beam while effecting a relative movement between the semiconductor substrate and the ion beam impinging on the semiconductor substrate.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: June 22, 2021
    Assignee: Infineon Technologies AG
    Inventors: Moriz Jelinek, Michael Kokot, Christian Krueger, Hans-Joachim Schulze, Werner Schustereder
  • Publication number: 20210183746
    Abstract: A method of manufacturing a semiconductor device includes: forming a base portion of a bonding pad on a semiconductor portion, the base portion further comprising a base layer; forming a main surface of the bonding pad, the main surface comprising a bonding region; bonding a bond wire or clip to the bonding region; and forming a supplemental structure directly on the base portion. The supplemental structure laterally adjoins the bond wire or clip or is laterally spaced apart from the bond wire or clip. A volume-related specific heat capacity of the supplemental structure is higher than a volume-related specific heat capacity of the base layer.
    Type: Application
    Filed: February 4, 2021
    Publication date: June 17, 2021
    Inventors: Anton Mauder, Hans-Joachim Schulze
  • Patent number: 11038028
    Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor substrate having opposing first and second main surfaces and first and second dopants. A covalent atomic radius of a material of the substrate is i) larger than a covalent atomic radius of the first dopant and smaller than that of the second dopant, or ii) smaller than the covalent atomic radius of the first dopant and larger than that of the second dopant. A vertical extension of the first dopant into the substrate from the first main surface ends at a bottom of a substrate portion at a first vertical distance to the first main surface. The method further includes forming a semiconductor layer on the first main surface, forming semiconductor device elements in the semiconductor layer, and reducing a thickness of the substrate by removing material from the second main surface at least up to the substrate portion.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: June 15, 2021
    Assignee: Infineon Technologies AG
    Inventors: Ingo Muri, Johannes Konrad Baumgartl, Oliver Hellmund, Jacob Tillmann Ludwig, Iris Moder, Thomas Christian Neidhart, Gerhard Schmidt, Hans-Joachim Schulze
  • Publication number: 20210175123
    Abstract: A method of splitting a semiconductor wafer includes: forming one or more epitaxial layers on the semiconductor wafer; forming a plurality of device structures in the one or more epitaxial layers; forming a metallization layer and/or a passivation layer over the plurality of device structures; attaching a carrier to the semiconductor wafer with the one or more epitaxial layers, the carrier protecting the plurality of device structures and mechanically stabilizing the semiconductor wafer; forming a separation region within the semiconductor wafer, the separation region having at least one altered physical property which increases thermo-mechanical stress within the separation region relative to the remainder of the semiconductor wafer; and applying an external force to the semiconductor wafer such that at least one crack propagates along the separation region and the semiconductor wafer splits into two separate pieces, one of the pieces retaining the plurality of device structures.
    Type: Application
    Filed: December 9, 2019
    Publication date: June 10, 2021
    Inventors: Christian Beyer, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze, Marko Swoboda
  • Patent number: 11031483
    Abstract: A method includes providing a first layer of epitaxial silicon carbide supported by a silicon carbide substrate, providing a second layer of epitaxial silicon carbide on the first layer, forming a plurality of semiconductor devices in the second layer, and separating the substrate from the second layer at the first layer. The first layer includes a plurality of voids.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: June 8, 2021
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Roland Rupp, Francisco Javier Santos Rodriguez
  • Publication number: 20210167195
    Abstract: A vertical power semiconductor device is described. The vertical power semiconductor device includes a semiconductor body having a first main surface and a second main surface opposite to the first main surface. A thickness of the semiconductor body between the first main surface and the second main surface ranges from 40 ?m to 200 ?m. Active device elements are formed in the semiconductor body at the first main surface. Edge termination elements at least partly surround the active device elements at the first main surface. A diffusion region extends into the semiconductor body from the second main surface. A doping concentration profile of the diffusion region decreases from a peak concentration Ns at the second main surface to a concentration Ns/e, e being Euler's number, over a vertical distance ranging from 1 ?m to 5 ?m.
    Type: Application
    Filed: November 20, 2020
    Publication date: June 3, 2021
    Inventors: Andre Brockmeier, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze
  • Publication number: 20210159316
    Abstract: A semiconductor component includes a semiconductor component, including: a merged PiN Schottky (MPS) diode structure in a SiC semiconductor body having a drift zone of a first conductivity type; an injection region of a second conductivity type adjoining a first surface of the SiC semiconductor body; a contact structure at the first surface, the contact structure forming a Schottky contact with the drift zone and electrically contacting the injection region; and a zone of the first conductivity type formed between the injection region and a second surface of the SiC semiconductor body, the second surface being situated opposite the first surface. The zone is at a maximal distance of 1 ?m from the injection region of the second conductivity type.
    Type: Application
    Filed: February 1, 2021
    Publication date: May 27, 2021
    Inventors: Thomas Basler, Hans-Joachim Schulze, Ralf Siemieniec
  • Publication number: 20210159115
    Abstract: Methods for processing a semiconductor substrate are proposed. An example of a method includes forming cavities in the semiconductor substrate by implanting ions through a first surface of the semiconductor substrate. The cavities define a separation layer in the semiconductor substrate. A semiconductor layer is formed on the first surface of the semiconductor substrate. Semiconductor device elements are formed in the semiconductor layer. The semiconductor substrate is separated along the separation layer into a first substrate part including the semiconductor layer and a second substrate part.
    Type: Application
    Filed: November 25, 2020
    Publication date: May 27, 2021
    Inventors: Werner SCHUSTEREDER, Alexander BREYMESSER, Mihai DRAGHICI, Tobias Franz Wolfgang HOECHBAUER, Wolfgang LEHNERT, Hans-Joachim SCHULZE, Marko David SWOBODA
  • Patent number: 11018051
    Abstract: A method includes: forming trenches extending from a surface along a vertical direction into a semiconductor body, facing trench sidewalls of two adjacent trenches laterally confining a mesa region of the semiconductor body along a first lateral direction; forming a body region in the mesa region, a surface of the body region in the mesa region at least partially forming the semiconductor body surface; forming a first insulation layer on the semiconductor body surface; subjecting the semiconductor body region to a tilted source implantation using at least one contact hole in the first insulation layer at least partially as a mask for forming a semiconductor source region in the mesa region. The tilted source implantation is tilted from the vertical direction by an angle of at least 10°. The semiconductor source region extends for no more than 80% of a width of the mesa region along the first lateral direction.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: May 25, 2021
    Assignee: Infineon Technologies Dresden GmbH & Co. KG
    Inventors: Markus Beninger-Bina, Matteo Dainese, Ingo Dirnstorfer, Erich Griebl, Johannes Georg Laven, Anton Mauder, Hans-Joachim Schulze
  • Patent number: 11018252
    Abstract: A power semiconductor transistor includes a semiconductor body having a front side and a backside with a backside surface. The semiconductor body includes a drift region of a first conductivity type and a field stop region of the first conductivity type. The field stop region is arranged between the drift region and the backside and includes, in a cross-section along a vertical direction from the backside to the front side, a concentration profile of donors of the first conductivity type that has: a first local maximum at a first distance from the backside surface, a front width at half maximum associated with the first local maximum, and a back width at half maximum associated with the first local maximum. The front width at half maximum is smaller than the back width at half maximum and amounts to at least 8% of the first distance.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: May 25, 2021
    Assignee: Infineon Technologies AG
    Inventors: Hans Peter Felsl, Moriz Jelinek, Volodymyr Komarnitskyy, Konrad Schraml, Hans-Joachim Schulze
  • Patent number: 11018249
    Abstract: A semiconductor component includes a semiconductor body having opposing first surface and second surfaces, and a side surface surrounding the semiconductor body. The semiconductor component also includes an active region including a first semiconductor region of a first conductivity type, which is electrically contacted via the first surface, and a second semiconductor region of a second conductivity type, which is electrically contacted via the second surface. The semiconductor component further includes an edge termination region arranged in a lateral direction between the first semiconductor region of the active region and the side surface, and includes a first edge termination structure and a second edge termination structure. The second edge termination structure is arranged in the lateral direction between the first edge termination structure and the side surface and extends from the first surface in a vertical direction more deeply into the semiconductor body than the first edge termination structure.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: May 25, 2021
    Assignee: Infineon Technologies AG
    Inventors: Anton Mauder, Hans-Joachim Schulze, Matteo Dainese, Elmar Falck, Franz-Josef Niedernostheide, Manfred Pfaffenlehner
  • Patent number: 11011409
    Abstract: A semiconductor device includes a first epitaxial layer, a second epitaxial layer disposed below the first epitaxial layer, a conductive layer disposed below and directly contacting the second epitaxial layer, and a plurality of spacers disposed between the second epitaxial layer and the conductive layer. The conductive layer includes a metal. The plurality of spacers include a bulk semiconductor material.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: May 18, 2021
    Assignee: Infineon Technologies AG
    Inventors: Oliver Hellmund, Ingo Muri, Johannes Baumgartl, Iris Moder, Thomas Christian Neidhart, Hans-Joachim Schulze
  • Patent number: 10998402
    Abstract: Crystal lattice vacancies are generated in a pretreated section of a semiconductor layer directly adjoining a process surface. Dopants are implanted at least into the pretreated section. A melt section of the semiconductor layer is heated by irradiating the process surface with a laser beam activating the implanted dopants at least in the melt section.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: May 4, 2021
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Alexander Breymesser, Hans-Joachim Schulze, Holger Schulze, Werner Schustereder