Abstract: A semiconductor device includes a SiC body having a first semiconductor area of a first conductivity type and a second semiconductor area of a second conductivity type. The first semiconductor area is electrically contacted with a first surface of the SiC body and forms a pn junction with the second semiconductor area. The first and second semiconductor areas are arranged on one another in a vertical direction perpendicular to the first surface. The first semiconductor area has first and second dopant species. An average dopant concentration of the first dopant species in a first part of the first semiconductor area adjoining the first surface is greater than an average dopant concentration of the second dopant species. An average dopant concentration of the second dopant species in a second part of the first semiconductor area adjoining the second semiconductor area is greater than a dopant concentration of the first dopant species.

Abstract: According to an embodiment of a semiconductor device, the semiconductor devices includes a metal structure electrically connected to a silicon carbide semiconductor body and a metal adhesion and barrier structure between the metal structure and the silicon carbide semiconductor body. The metal adhesion and barrier structure includes a layer comprising titanium and tungsten.

Abstract: A semiconductor substrate includes a base portion, an auxiliary layer and a surface layer. The auxiliary layer is formed on the base portion. The surface layer is formed on the auxiliary layer. The surface layer is in contact with a first main surface of the semiconductor substrate. The auxiliary layer has a different electrochemical dissolution efficiency than the base portion and the surface layer. At least a portion of the auxiliary layer and at least a portion of the surface layer are converted into a porous structure. Subsequently, an epitaxial layer is formed on the first main surface.

Abstract: An embodiment of a semiconductor device includes a silicon carbide semiconductor body including source and body regions of opposite conductivity types. A trench structure extends from a first surface into the silicon carbide semiconductor body along a vertical direction, and includes a gate electrode and a gate dielectric. A contact is electrically connected to the source region at the first surface. The source region includes a first source sub-region directly adjoining the contact at a source contact area of the first surface, a second source sub-region, and a third source sub-region. The second sub-region is arranged between the first and third sub-regions along the vertical direction. A doping concentration profile along the vertical direction of the source region includes a doping concentration minimum in the second sub-region and a doping concentration maximum in the third sub-region. Each of the second and third sub-regions overlaps with the source contact area.

Abstract: A semiconductor device includes: a semiconductor substrate having a bulk oxygen concentration of at least 6×1017 cm?3; an epitaxial layer on a first side of the semiconductor substrate, the epitaxial layer and the semiconductor substrate having a common interface; a superjunction semiconductor device structure in the epitaxial layer; and an interface region extending from the common interface into the semiconductor substrate to a depth of at least 10 ?m. A mean oxygen concentration of the interface region is lower than the bulk oxygen concentration of the semiconductor substrate.

Abstract: A semiconductor device includes a first IGBT cell having a second-type doped drift zone and a desaturation semiconductor structure for desaturating a charge carrier concentration in the first IGBT cell. The desaturation semiconductor structure includes a first-type doped region forming a pn-junction with the drift zone and two trenches arranged in the first-type doped region and arranged beside the first IGBT cell in a lateral direction. The two trenches confine a mesa region including a first-type doped desaturation channel region and a first-type doped body region at least in the lateral direction. The desaturation channel region and the body region adjoin each other, and the desaturation channel region is a depletable region. Related methods of manufacture are also described.

Abstract: Forming a semiconductor arrangement includes providing a first semiconductor layer having a first surface, forming a first plurality of trenches in the first surface of the first semiconductor layer, each of the trenches in the first plurality having first and second sidewalls that extend from the first surface to a bottom of the respective trench, implanting first type dopant atoms into the first and second sidewalls of each of the trenches in the first plurality, implanting second type dopant atoms into the first and second sidewalls of each of the trenches in the first plurality, and annealing the semiconductor arrangement to simultaneously activate the first type dopant atoms and the second type dopant atoms.

Abstract: In accordance with a method of manufacturing CZ silicon wafers, a parameter of at least two of the CZ silicon wafers is measured. A group of the CZ silicon wafers falling within a tolerance of a target specification is determined. The group of the CZ silicon wafers is divided into sub-groups taking into account the measured parameter. An average value of the parameter of the CZ silicon wafers of each sub-group differs among the sub-groups, and a tolerance of the parameter of the CZ silicon wafers of each sub-group is smaller than a tolerance of the parameter of the target specification. A labeling configured to distinguish between the CZ silicon wafers of different sub-groups is prepared. The CZ silicon wafers falling within the tolerance of the target specification are packaged.

Abstract: A method of Czochralski growth of a silicon ingot includes melting a mixture of silicon material and an n-type dopant material in a crucible. The silicon ingot is extracted from the molten silicon over an extraction time period. Boron is added to the molten silicon over at least part of the extraction time period.

Abstract: One example describes a method of manufacturing Czochralski (CZ) silicon wafers. The method includes slicing an n-type CZ silicon ingot to form a plurality of CZ silicon wafers, determining a boron concentration of each CZ silicon wafer, dividing the CZ silicon wafers into sub-groups based on the boron concentration, wherein an average value of the boron concentration differs among the sub-groups, and labeling each sub-group of CZ silicon wafers with a different label which is indicative of the boron concentration.

Abstract: A semiconductor device includes a plurality of first and second stripe-shaped cell trench structures formed in a semiconductor substrate and extending lengthwise in parallel with one another. Each stripe-shaped cell trench structure includes a buried electrode and an insulator layer between the buried electrode and the semiconductor substrate. A recess is formed in the insulator layer along a sidewall of one or more of the first stripe-shaped cell trench structures and vertically extends to a corresponding heavily doped contact zone. An electrically conductive material disposed in each recess contacts the corresponding buried electrode, a corresponding source zone and a corresponding heavily doped contact zone at the sidewall. Two or more of the first stripe-shaped cell trench structures are interposed between neighboring ones of the second stripe-shaped cell trench structures. Source zones alternate with portions of body zones in a lateral direction parallel to the stripe-shaped cell trench structures.

Abstract: A method of manufacturing a semiconductor device includes forming an auxiliary mask including a plurality of mask openings on a main surface of a crystalline semiconductor substrate. A porous structure is formed in the semiconductor substrate. The porous structure includes a porous layer at a distance to the main surface and porous columns that extend from the porous layer into direction of the main surface and that are laterally separated from each other by a non-porous portion. A non-porous device layer is formed on the non-porous portion and on the porous columns.

Abstract: Devices and methods are provided where a control terminal resistance of a transistor device is set depending on operating conditions within a specified range of operating conditions.

Abstract: A wide band gap semiconductor device includes a first doping region of a first conductivity type and a second doping region of a second conductivity type. A drift portion of the second doping region has a first average net doping concentration lower than 1e17 cm?3. A highly doped portion of the second doping region has a second average net doping concentration higher than 5e18 cm?3. A compensation portion of the second doping region located between the drift and highly doped portions extends from a first area with a net doping concentration higher than 1e16 cm?3 and lower than 1e17 cm?3 to a second area with a net doping concentration higher than 5e18 cm?3. A maximum gradient of the net doping concentration within at least a part of the compensation portion extending from the second area towards the first area for at least 100 nm is lower than 5e22 cm?4.

Abstract: A semiconductor device includes a silicon carbide body that includes a first section and a second section. The first section is adjacent to the second section. A drift region is formed in the first section and the second section. A lattice defect region is in a portion of the drift region in the second section. A first density of lattice defects, which include interstitials and vacancies in the lattice defect region, is at least double a second density of lattice defects, which include interstitials and vacancies in a portion of the drift region outside the lattice defect region.

Abstract: A power semiconductor device includes a semiconductor body having front and back sides. The semiconductor body includes drift, field stop and emitter adjustment regions each of a first conductivity type. The field stop region is arranged between the drift region and the backside and has dopants of the first conductivity type at a higher dopant concentration than the drift region. The emitter adjustment region is arranged between the field stop region and the backside and has dopants of the first conductivity type at a higher dopant concentration than the field stop region. The semiconductor body has a concentration of interstitial oxygen of at least 1E17 cm?3. The field stop region includes a region where the dopant concentration is higher than that in the drift region at least by a factor of three. At least 20% of the dopants of the first conductivity type in the region are oxygen-induced thermal donors.

Abstract: A power inverter includes a bridge circuit including a first half-bridge and a second half-bridge, each half-bridge including a high-side device and a low-side device, and a gate driver circuit connected with each gate of the high-side device and low-side power device of the first and second half-bridges and operable to provide each gate with a respective voltage to control operation of the respective power device. The gate driver is operable to provide a first voltage which is higher than a first threshold voltage of the respective power device, and a second voltage which is higher than a surge threshold of the respective power device. The surge threshold is higher than the first threshold and defines the onset of a surge current operation area of the respective power device at which the power device becomes conducts a surge current that is larger than the rated current of the device.

Abstract: A semiconductor device and method is disclosed. In one example, the method for forming a semiconductor device includes forming a trench extending from a front side surface of a semiconductor substrate into the semiconductor substrate. The method includes forming of material to be structured inside the trench. Material to be structured is irradiated with a tilted reactive ion beam at a non-orthogonal angle with respect to the front side surface such that an undesired portion of the material to be structured is removed due to the irradiation with the tilted reactive ion beam while an irradiation of another portion of the material to be structured is masked by an edge of the trench.

Abstract: A module is disclosed. In one example, the module includes a carrier, an at least partially thermally conductive and electrically insulating body mounted on only a part of a main surface of the carrier, an at least partially electrically conductive redistribution structure on the thermally conductive and electrically insulating body, an electronic chip mounted on the redistribution structure and above the thermally conductive and electrically insulating body, and an encapsulant encapsulating at least part of the carrier, at least part of the thermally conductive and electrically insulating body, at least part of the redistribution structure, and at least part of the electronic chip.

Abstract: A semiconductor device is described in which a conductive channel is present along an active gate trench of the device when a gate potential is at an on-voltage, whereas no conductive channel is present along an inactive gate trench of the device for the same gate potential condition.