Patents by Inventor Hans-Joachim Schulze

Hans-Joachim Schulze has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10497801
    Abstract: A method of manufacturing a semiconductor device includes forming a profile of net doping in a drift zone of a semiconductor body by multiple irradiations with protons and generating hydrogen-related donors by annealing the semiconductor body. At least 50% of a vertical extension of the drift zone between first and second sides of the semiconductor body is undulated and includes multiple doping peak values between 1×1013 cm?3 and 5×1014 cm?3.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: December 3, 2019
    Assignee: Infineon Technologies AG
    Inventors: Elmar Falck, Andreas Haertl, Manfred Pfaffenlehner, Francisco Javier Santos Rodriguez, Daniel Schloegl, Hans-Joachim Schulze, Andre Stegner, Johannes Georg Laven
  • Publication number: 20190362972
    Abstract: A method for processing a silicon carbide wafer includes implanting ions into the silicon carbide wafer to form an absorption layer in the silicon carbide wafer. The absorption coefficient of the absorption layer is at least 100 times the absorption coefficient of silicon carbide material of the silicon carbide wafer outside the absorption layer, for light of a target wavelength. The silicon carbide wafer is split along the absorption layer at least by irradiating the silicon carbide wafer with light of the target wavelength to obtain a silicon carbide device wafer and a remaining silicon carbide wafer.
    Type: Application
    Filed: May 24, 2019
    Publication date: November 28, 2019
    Inventors: Hans-Joachim Schulze, Alexander Breymesser, Guenter Denifl, Mihai Draghici, Bernhard Goller, Tobias Franz Wolfgang Hoechbauer, Wolfgang Lehnert, Roland Rupp, Werner Schustereder
  • Publication number: 20190363057
    Abstract: A method for processing a semiconductor wafer is proposed. The method may include reducing a thickness of the semiconductor wafer. A carrier structure is placed on a first side of the semiconductor wafer, e.g. before or after reducing the thickness of the semiconductor wafer. The method further includes providing a support structure on a second side of the semiconductor wafer opposite to the first side, e.g. after reducing the thickness of the semiconductor wafer. Methods for welding a support structure onto a semiconductor wafer are proposed. Further, semiconductor composite structures with support structures welded onto a semiconductor wafer are proposed.
    Type: Application
    Filed: May 24, 2019
    Publication date: November 28, 2019
    Inventors: Francisco Javier Santos Rodriguez, Alexander Breymesser, Erich Griebl, Michael Knabl, Matthias Kuenle, Andreas Moser, Roland Rupp, Hans-Joachim Schulze, Sokratis Sgouridis, Stephan Voss
  • Patent number: 10490656
    Abstract: A charge-compensation semiconductor device includes a source metallization spaced apart from a gate metallization, and a semiconductor body including opposing first and second sides, a drift region, a plurality of body regions adjacent the first side and each forming a respective first pn-junction with the drift region, and a plurality of compensation regions arranged between the second side and the body regions. Each compensation region forms a respective further pn-junction with the drift region. A plurality of gate electrodes in Ohmic connection with the gate metallization is arranged adjacent the first side and separated from the body regions and the drift region by a dielectric region. A resistive current path is formed between one of the gate electrodes and a first one of the compensation regions, or between the first one of the compensation regions and a further metallization spaced apart from the source metallization and the gate metallization.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: November 26, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Armin Willmeroth, Franz Hirler, Anton Mauder, Frank Dieter Pfirsch, Hans-Joachim Schulze, Uwe Wahl
  • Publication number: 20190355815
    Abstract: The disclosure relates to a semiconductor component having an SiC semiconductor body and a first load terminal on a first surface of the SiC semiconductor body. A second load terminal is formed on a second surface of the SiC semiconductor body opposite the first surface. The semiconductor component has a drift zone of a first conductivity type in the SiC semiconductor body and a first semiconductor area of a second conductivity type which is electrically connected to the first load terminal. A pn junction between the drift zone and the first semiconductor area defines a voltage blocking strength of the semiconductor component.
    Type: Application
    Filed: May 17, 2019
    Publication date: November 21, 2019
    Inventors: Thomas Basler, Rudolf Elpelt, Hans-Joachim Schulze
  • Publication number: 20190355841
    Abstract: A power semiconductor device includes a semiconductor body having a front side coupled to a first load terminal structure and a backside coupled to a second load terminal structure. A front side structure arranged at the front side is at least partially included in the semiconductor body and defines a front side active region configured to conduct a load current between the load terminal structures. The front side structure includes first and second lateral edge portions and a first corner portion that forms a transition between the lateral edge portions. A drift region included in the semiconductor body is configured to carry the load current. A backside emitter region arranged in the semiconductor body in contact with the second load terminal has a net dopant concentration higher than a net dopant concentration of the drift region.
    Type: Application
    Filed: May 16, 2019
    Publication date: November 21, 2019
    Inventors: Benedikt Stoib, Hans-Joachim Schulze, Max Christian Seifert
  • Patent number: 10483384
    Abstract: A transistor device includes a first emitter region of a first doping type, a second emitter region of a second doping type, a body of the second doping type, a drift region of the first doping type, a field-stop region of the first doping type, at least one boost structure, and a gate electrode. The boost structure is arranged between the field-stop region and the second emitter region. The at least one boost structure includes a base region of the first doping type and at least one auxiliary emitter region of the second doping type separated from the second emitter region by the base region. An overall dopant dose in the drift region and the field-stop region in a current flow direction of the transistor device is higher than a breakthrough charge of a semiconductor material of the drift region and the field-stop region.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: November 19, 2019
    Assignee: Infineon Technologies AG
    Inventors: Riteshkumar Bhojani, Franz-Josef Niedernostheide, Hans-Joachim Schulze, Josef Lutz, Roman Baburske
  • Publication number: 20190348506
    Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor substrate having opposing first and second main surfaces and first and second dopants. A covalent atomic radius of a material of the substrate is i) larger than a covalent atomic radius of the first dopant and smaller than that of the second dopant, or ii) smaller than the covalent atomic radius of the first dopant and larger than that of the second dopant. A vertical extension of the first dopant into the substrate from the first main surface ends at a bottom of a substrate portion at a first vertical distance to the first main surface. The method further includes forming a semiconductor layer on the first main surface, forming semiconductor device elements in the semiconductor layer, and reducing a thickness of the substrate by removing material from the second main surface at least up to the substrate portion.
    Type: Application
    Filed: May 8, 2019
    Publication date: November 14, 2019
    Inventors: Ingo Muri, Johannes Konrad Baumgartl, Oliver Hellmund, Jacob Tillmann Ludwig, Iris Moder, Thomas Christian Neidhart, Gerhard Schmidt, Hans-Joachim Schulze
  • Publication number: 20190348328
    Abstract: A method for processing a wide band gap semiconductor wafer is proposed. The method includes depositing a non-monocrystalline support layer at a back side of a wide band gap semiconductor wafer, depositing an epitaxial layer at a front side of the wide band gap semiconductor wafer, and splitting the wide band gap semiconductor wafer along a splitting region to obtain a device wafer including at least a part of the epitaxial layer, and a remaining wafer including the non-monocrystalline support layer.
    Type: Application
    Filed: May 13, 2019
    Publication date: November 14, 2019
    Inventors: Francisco Javier Santos Rodriguez, Guenter Denifl, Tobias Franz Wolfgang Hoechbauer, Martin Huber, Wolfgang Lehnert, Roland Rupp, Hans-Joachim Schulze
  • Patent number: 10475910
    Abstract: A semiconductor device includes an insulated gate bipolar transistor (IGBT) arrangement having a first configuration region of emitter-side insulated gate bipolar transistor structures, a second configuration region of emitter-side insulated gate bipolar transistor structures, a collector layer and a drift layer. The drift layer is arranged between the collector layer and the emitter-side insulated gate bipolar transistor structures of the first configuration region and the second configuration region. The collector layer includes at least a first doping region laterally adjacent to a second doping region, the doping regions having different charge carrier life times, different conductivity types or different doping concentrations. The first configuration region is located with at least a partial lateral overlap to the first doping region, and the second configuration region is located with at least a partial lateral overlap to the second doping region.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: November 12, 2019
    Assignee: Infineon Technologies AG
    Inventors: Johannes Georg Laven, Hans-Joachim Schulze, Roman Baburske
  • Patent number: 10475911
    Abstract: Some embodiments relate to a semiconductor device that includes a body region of a field effect transistor structure formed in a semiconductor substrate between a drift region of the field effect transistor structure and a source region of the field effect transistor structure. The semiconductor substrate includes chalcogen atoms at an atom concentration of less than 1×1013 cm?3 at a p-n junction between the body region and the drift region, and at least part of the source region includes chalcogen atoms at an atom concentration of greater than 1×1014 cm?3. Additional semiconductor device embodiments and corresponding methods of manufacture are described.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: November 12, 2019
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Philip Christoph Brandt, Andre Rainer Stegner
  • Patent number: 10475881
    Abstract: Crystal lattice vacancies are generated in a pretreated section of a semiconductor layer directly adjoining a process surface. Dopants are implanted at least into the pretreated section. A melt section of the semiconductor layer is heated by irradiating the process surface with a laser beam activating the implanted dopants at least in the melt section.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: November 12, 2019
    Assignee: Infineon Technologies AG
    Inventors: Alexander Breymesser, Hans-Joachim Schulze, Holger Schulze, Werner Schustereder
  • Patent number: 10475743
    Abstract: According to an embodiment of a semiconductor device, the semiconductor devices includes a metal structure electrically connected to a semiconductor body and a metal adhesion and barrier structure between the metal structure and the semiconductor body. The metal adhesion and barrier structure includes a first layer having titanium and tungsten, and a second layer having titanium, tungsten, and nitrogen on the first layer having titanium and tungsten.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: November 12, 2019
    Assignee: Infineon Technologies AG
    Inventors: Frank Hille, Ravi Keshav Joshi, Michael Fugger, Oliver Humbel, Thomas Laska, Matthias Mueller, Roman Roth, Carsten Schaeffer, Hans-Joachim Schulze, Holger Schulze, Juergen Steinbrenner, Frank Umbach
  • Publication number: 20190341447
    Abstract: A semiconductor component has a gate structure that extends from a first surface into an SiC semiconductor body. A body area in the SiC semiconductor body adjoins a first side wall of the gate structure. A first shielding area and a second shielding area of the conductivity type of the body area have at least twice as high a level of doping as the body area. A diode area forms a Schottky contact with a load electrode between the first shielding area and the second shielding area.
    Type: Application
    Filed: May 6, 2019
    Publication date: November 7, 2019
    Inventors: Ralf Siemieniec, Thomas Aichinger, Thomas Basler, Wolfgang Bergner, Rudolf Elpelt, Romain Esteve, Michael Hell, Daniel Kueck, Caspar Leendertz, Dethard Peters, Hans-Joachim Schulze
  • Patent number: 10468148
    Abstract: In various embodiments, a method of processing one or more semiconductor wafers is provided. The method includes positioning the one or more semiconductor wafers in an irradiation chamber, generating a neutron flux in a spallation chamber coupled to the irradiation chamber, moderating the neutron flux to produce a thermal neutron flux, and exposing the one or more semiconductor wafers to the thermal neutron flux to thereby induce the creation of dopant atoms in the one or more semiconductor wafers.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: November 5, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Markus Bina, Hans-Joachim Schulze, Werner Schustereder
  • Patent number: 10461739
    Abstract: Transistor devices are provided. A transistor device includes a unipolar transistor coupled between a first terminal and a second terminal; and a bipolar transistor coupled in parallel to the unipolar transistor between the first terminal and the second terminal. The bipolar transistor is configured to carry a majority of a current flowing through the transistor device when at least one of the current or a control voltage controlling the unipolar transistor and the bipolar transistor exceeds a predetermined threshold. The bipolar transistor is further configured to have a threshold voltage higher than a threshold voltage of the unipolar transistor, and a difference between the threshold voltage of the bipolar transistor and the threshold voltage of the unipolar transistor is at least 1 V.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: October 29, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Thomas Basler, Roman Baburske, Johannes Georg Laven, Franz-Josef Niedernostheide, Hans-Joachim Schulze
  • Publication number: 20190319123
    Abstract: A semiconductor device is described in which a conductive channel is present along an active gate trench of the device when a gate potential is at an on-voltage, whereas no conductive channel is present along an inactive gate trench of the device for the same gate potential condition.
    Type: Application
    Filed: June 28, 2019
    Publication date: October 17, 2019
    Inventors: Maria Cotorogea, Frank Wolter, Hans-Joachim Schulze, Franz-Josef Niedernostheide, Yvonne Gawlina-Schmidl
  • Publication number: 20190319091
    Abstract: A method of forming a semiconductor device includes forming a trench in a semiconductor body; at least partially filling the trench with a filling material, the filling material; introducing dopants into a portion of the filling material, where the dopants have a first diffusion coefficient relative to the filling material and have a second diffusion coefficient relative to the semiconductor body, where the first diffusion coefficient is greater than the second diffusion coefficient, and where a ratio of the first diffusion coefficient to the second diffusion coefficient is greater than 10; and applying thermal processing to the semiconductor body configured to spread the dopants in the filling material along a vertical direction between a bottom side and a top side of the filling material by a diffusion process.
    Type: Application
    Filed: June 28, 2019
    Publication date: October 17, 2019
    Applicant: Infineon Technologies AG
    Inventors: Reinhard PLOSS, Hans-Joachim SCHULZE
  • Publication number: 20190318996
    Abstract: A molding compound and a semiconductor arrangement with a molding compound are disclosed. The molding compound includes a matrix and a filler including filler particles. The filler particles each include a core with an electrically conducting or a semiconducting material and an electrically insulating cover.
    Type: Application
    Filed: April 16, 2019
    Publication date: October 17, 2019
    Inventors: Anton Mauder, Oliver Hellmund, Peter Irsigler, Hanno Melzner, Stefan Miethaner, Sebastian Schmidt, Hans-Joachim Schulze
  • Patent number: 10439025
    Abstract: A first part of a semiconductor body is provided. Impurities are introduced into the first part of the semiconductor body, The impurities act as recombination centers in the semiconductor body and form a recombination Zone, and the impurities include at least a heavy metal. A second part of the semiconductor body is epitaxially produced on the first part after introducing the impurities in the first part. During epitaxially producing the second part of the semiconductor body on the first part of the semiconductor body, impurities in the first part of the semiconductor body are diffused to the second part of the semiconductor body.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: October 8, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Frank Pfirsch, Hans-Joachim Schulze