Abstract: An integrated circuit product is disclosed including an SOI structure including a bulk semiconductor substrate, a buried insulation layer positioned on the bulk semiconductor substrate and a semiconductor layer positioned on the insulation layer, wherein, in a first region of the SOI structure, the semiconductor layer and the buried insulation layer are removed and, in a second region of the SOI structure, the semiconductor layer and the buried insulation layer are present above the bulk semiconductor substrate. The product further includes a semiconductor bulk device comprising a first gate structure positioned on the bulk semiconductor substrate in the first region and an SOI semiconductor device comprising a second gate structure positioned on the semiconductor layer in the second region, wherein the first and second gate structures have a final gate height substantially extending to a common height level above an upper surface of the bulk semiconductor substrate.

Abstract: A semiconductor device with a metal-containing layer, a first semiconductor layer, that is formed on top of the metal-containing layer, and a resistor that is formed in the metal-containing layer and that is contacted through the first semiconductor layer is provided. Furthermore, a method of manufacturing a semiconductor device is provided, wherein the method comprises manufacturing of a resistor with the following steps: formation of a metal-containing layer over a wafer, particularly a SOI wafer, formation of a first semiconductor layer on top of the metal-containing layer and formation of a contact through the semiconductor layer to the metal-containing layer.

Abstract: A semiconductor structure includes a substrate, at least one electrically conductive pillar provided over the substrate and an electrically conductive structure provided over the substrate. The electrically conductive pillar includes an inner portion and an outer layer that is provided below the inner portion and lateral to the inner portion. The electrically conductive structure also includes an inner portion and an outer layer that is provided below the inner portion and lateral to the inner portion. The electrically conductive structure annularly encloses each of the at least one electrically conductive pillar. The outer layer of each of the at least one electrically conductive pillar contacts the outer layer of the electrically conductive structure. The outer layer of the at least one electrically conductive pillar and the outer layer of the electrically conductive structure are formed of different metallic materials.

Abstract: A semiconductor device includes an active region formed in a semiconductor substrate, a gate structure disposed over the active region, source/drain regions formed in the active region in alignment with the gate structure, and a buried insulating material region disposed in the active region under the gate structure. The buried insulating material region is surrounded by the active region and borders a channel region in the active region below the gate structure along a depth of the active region. The source/drain regions have a depth greater than a top surface of the buried insulating material region.

Abstract: A method of forming a semiconductor device structure includes providing a substrate with a semiconductor-on-insulator (SOI) configuration, the SOI substrate comprising a semiconductor layer formed on a buried oxide (BOX) layer which is disposed on a semiconductor bulk substrate, forming trench isolation structures delineating a first region and a second region within the SOI substrate, removing the semiconductor layer and the BOX layer in the first region for exposing the semiconductor bulk substrate within the first region, forming a first semiconductor device with an electrode in and over the exposed semiconductor bulk substrate in the first region, forming a second semiconductor device in the second region, the second semiconductor device comprising a gate structure disposed over the semiconductor layer and the BOX layer in the second region, and performing a polishing process for defining a common height level to which the electrode and the gate structure substantially extend.

Abstract: The present disclosure provides methods of forming a masking pattern and a semiconductor device structure, wherein printed half pitches of, for example, about 20 nm or less may be formed. A method of forming a masking pattern is provided wherein an unpatterned mask layer is formed over a semiconductor device structure provided in and on an upper surface of a semiconductor substrate, and the unpatterned mask layer is patterned for forming the masking pattern over the semiconductor device structure. The unpatterned mask layer is patterned by forming a dummy pattern having at least one recess on the unpatterned mask layer, forming a first sidewall spacer structure adjacent to sidewalls of the recess, removing the dummy pattern, forming a second sidewall spacer structure on the first sidewall spacer structure, removing the first sidewall spacer structure, and etching the unpatterned mask layer in alignment with the second sidewall spacer structure.

Abstract: A semiconductor structure includes a substrate, at least one electrically conductive pillar provided over the substrate and an electrically conductive structure provided over the substrate. The electrically conductive pillar includes an inner portion and an outer layer that is provided below the inner portion and lateral to the inner portion. The electrically conductive structure also includes an inner portion and an outer layer that is provided below the inner portion and lateral to the inner portion. The electrically conductive structure annularly encloses each of the at least one electrically conductive pillar. The outer layer of each of the at least one electrically conductive pillar contacts the outer layer of the electrically conductive structure. The outer layer of the at least one electrically conductive pillar and the outer layer of the electrically conductive structure are formed of different metallic materials.

Abstract: The present disclosure provides a semiconductor device including an SOI substrate comprising an active semiconductor layer disposed on a buried insulating material layer, which is in turn formed on a base semiconductor material. The semiconductor device further includes a gate structure formed on the active semiconductor layer, source/drain regions provided at opposing sides of the gate structure, and a contact structure having contact elements for contacting the source/drain regions. Herein, the contact elements are disposed at opposing sides of the gate structure and are in alignment therewith. Furthermore, one of the contact elements extends through the buried insulating material layer and is in electrical contact with the base semiconductor material.

Abstract: A method of manufacturing a semiconductor device including a capacitor structure is provided, including the steps of providing an SOI wafer comprising a substrate, a buried oxide (BOX) layer formed over the substrate and a semiconductor layer formed over the BOX layer, removing the semiconductor layer in a first region of the wafer to expose the BOX layer, forming a dielectric layer over the exposed BOX layer in the first region, and forming a conductive layer over the dielectric layer. Moreover, a semiconductor device including a capacitor formed on a wafer is provided, wherein the capacitor comprises a first capacitor electrode comprising a doped semiconductor substrate of the wafer, a capacitor insulator comprising an ultra-thin BOX layer of the wafer and a high-k dielectric layer formed on the ultra-thin BOX layer, and a second capacitor electrode comprising a conductive layer formed over the high-k dielectric layer.

Abstract: A method of forming a semiconductor device structure includes providing a substrate with a semiconductor-on-insulator (SOI) configuration, the SOI substrate comprising a semiconductor layer formed on a buried oxide (BOX) layer which is disposed on a semiconductor bulk substrate, forming trench isolation structures delineating a first region and a second region within the SOI substrate, removing the semiconductor layer and the BOX layer in the first region for exposing the semiconductor bulk substrate within the first region, forming a first semiconductor device with an electrode in and over the exposed semiconductor bulk substrate in the first region, forming a second semiconductor device in the second region, the second semiconductor device comprising a gate structure disposed over the semiconductor layer and the BOX layer in the second region, and performing a polishing process for defining a common height level to which the electrode and the gate structure substantially extend.

Abstract: A method of manufacturing a semiconductor device is provided, including forming a gate electrode of a dummy transistor device on a semiconductor substrate, forming a high-k material layer over and adjacent to the gate electrode and forming a metal layer on the high-k material layer over and adjacent to the gate electrode to form a capacitor.

Abstract: The present disclosure provides in some aspects a semiconductor device and a method of forming a semiconductor device. According to some illustrative embodiments herein, the semiconductor device includes an active region formed in a semiconductor substrate, a gate structure disposed over the active region, source/drain regions formed in the active region in alignment with the gate structure, and an insulating material region buried into the active region under the gate structure, wherein the insulating material region is surrounded by the active region and borders a channel region in the active region below the gate structure along a depth direction of the active region.

Abstract: The present disclosure provides in some aspects a semiconductor device and a method of forming a semiconductor device. According to some illustrative embodiments herein, the semiconductor device includes an active region formed in a semiconductor substrate, a gate structure disposed over the active region, source/drain regions formed in the active region in alignment with the gate structure, and an insulating material region buried into the active region under the gate structure, wherein the insulating material region is surrounded by the active region and borders a channel region in the active region below the gate structure along a depth direction of the active region.

Abstract: A method of manufacturing a semiconductor device is provided, including forming a gate electrode of a dummy transistor device on a semiconductor substrate, forming a high-k material layer over and adjacent to the gate electrode and forming a metal layer on the high-k material layer over and adjacent to the gate electrode to form a capacitor.

Abstract: Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming an implant mask overlying a dummy gate, where the implant mask produces a masked dummy gate and an exposed dummy gate. Ions are implanted into the exposed dummy gate, and the implant mask is removed. The masked dummy gate is etched with an etchant selective to the masked dummy gate over the exposed dummy gate to form a trench, and the trench is filled with a conductive material.

Abstract: Methods and apparatus are provided for an integrated circuit with a transistor and a resistor. The method includes depositing a first dielectric layer over the transistor and the resistor, followed by an amorphous silicon layer. The amorphous silicon layer is implanted over the resistor to produce an etch mask, and the amorphous silicon layer and first dielectric layer are removed over the transistor. A contact location on the transistor is then silicided.

Abstract: When forming metallization layers of advanced semiconductor devices, one often has to fill apertures with a high aspect ratio with a metal, such as copper. The present disclosure provides a convenient method for forming apertures with a high aspect ratio in an insulating layer. This insulating layer may have been deposited on the surface of a semiconductor device. The proposed method relies on an ion implantation step performed on the insulating layer, followed by an etch, which is preferably a wet etch.

Abstract: Methods and apparatus are provided for an integrated circuit with a transistor and a resistor. The method includes depositing a first dielectric layer over the transistor and the resistor, followed by an amorphous silicon layer. The amorphous silicon layer is implanted over the resistor to produce an etch mask, and the amorphous silicon layer and first dielectric layer are removed over the transistor. A contact location on the transistor is then silicided.

Abstract: When forming metallization layers of advanced semiconductor devices, one often has to fill apertures with a high aspect ratio with a metal, such as copper. The present disclosure provides a convenient method for forming apertures with a high aspect ratio in an insulating layer. This insulating layer may have been deposited on the surface of a semiconductor device. The proposed method relies on an ion implantation step performed on the insulating layer, followed by an etch, which is preferably a wet etch.

Abstract: One illustrative method disclosed herein includes forming a structure above a semiconductor substrate, performing a conformal deposition process to form a layer of undoped spacer material above the structure, performing an angled ion implant process to form a region of doped spacer material in the layer of undoped spacer material while leaving other portions of the layer of undoped spacer material undoped, and, after performing the angled ion implant process, performing at least one etching process that removes the undoped portions of the layer of undoped spacer material and thereby results in a sidewall spacer comprised of the doped spacer material positioned adjacent at least one side, but not all sides, of the structure.