Abstract: One illustrative method disclosed herein includes forming a structure above a semiconductor substrate, performing a conformal deposition process to form a layer of undoped spacer material above the structure, performing an angled ion implant process to form a region of doped spacer material in the layer of undoped spacer material while leaving other portions of the layer of undoped spacer material undoped, and, after performing the angled ion implant process, performing at least one etching process that removes the undoped portions of the layer of undoped spacer material and thereby results in a sidewall spacer comprised of the doped spacer material positioned adjacent at least one side, but not all sides, of the structure.

Abstract: One embodiment relates to an integrated circuit formed on a semiconductor body having interconnect between source/drain regions of a first and second transistor. The interconnect includes a metal body arranged underneath the surface of the semiconductor body. A contact element establishes electrical contact between the metal body and the source/drain regions of the first and second transistor. The contact element extends along a connecting path between the source/drain regions of the first and second transistors. Other methods, devices, and systems are also disclosed.

Abstract: A method of forming a semiconductor device includes depositing a fill material (4) on a substrate portion (2) and on a dielectric layer (3) being disposed on the substrate (1) and having an opening (10) located above the substrate portion (2), removing the fill material (4) disposed above the dielectric layer (3), thereby leaving an exposed top surface (6) of the dielectric layer (3) and residual fill material (15) within the opening (10), forming a hard mask material (5) on the exposed top surface (6) of the dielectric layer (3) and on the residual fill material (15), patterning the hard mask material (5) for forming a hard mask (25) having trenches (8a, 8b) extending along a lateral direction (X) and exposing portions of the residual fill material (15) adjacent to the dielectric layer (3) and portions of the dielectric layer (3) adjacent to the residual fill material (15), anisotropically etching the dielectric layer (3), the residual fill material (15) and the substrate (1) selectively to the hard mask (5)

Abstract: An integrated circuit is manufactured from a semiconductor substrate having trenches with first and second sidewalls facing each other and a conductive line arranged in a bottom region of the trenches. At least the bottom region of the trenches is lined with an insulative material between the conductive line and the substrate. A first sacrificial layer is formed above the conductive line adjacent the first and second sidewalls. The trenches are filled with one or more additional sacrificial layers having a different etch selectivity than the first sacrificial layer. A portion of the one or more additional sacrificial layers and a portion of the insulative material are selectively removed to the first sacrificial layer so that the substrate is exposed below the first sacrificial layer along the first trench sidewalls and covered by the insulative material along the second trench sidewalls.

Abstract: One embodiment relates to an integrated circuit formed on a semiconductor body having interconnect between source/drain regions of a first and second transistor. The interconnect includes a metal body arranged underneath the surface of the semiconductor body. A contact element establishes electrical contact between the metal body and the source/drain regions of the first and second transistor. The contact element extends along a connecting path between the source/drain regions of the first and second transistors. Other methods, devices, and systems are also disclosed.

Abstract: In a method for producing a trench transistor, a substrate of a first conduction type is provided and a trench in the substrate and a gate dielectric in the trench are formed. A first conductive filling in the trench as a gate electrode on the gate dielectric and first source and drain regions are formed. An etched-back first conductive filling is produced by etching back the first conductive filling down to a depth below the first source and drain regions and second source and drain regions are formed. The second source and drain regions adjoin the first source and drain regions and extend to a depth at least as far as the etched-back first conductive filling. An insulation spacer above the etched-back first conductive filling is formed in the trench and a second conductive filling is provided in the trench as an upper part of the gate electrode.

Abstract: A method of fabricating an integrated device on a substrate with an exposed surface region is disclosed. One embodiment provides introducing a first component into the exposed surface region of the substrate. A material is provided on the exposed surface region. The material on the exposed surface region is cured and the first component release from the exposed surface region of the substrate.

Abstract: A method of forming a semiconductor device includes depositing a fill material (4) on a substrate portion (2) and on a dielectric layer (3) being disposed on the substrate (1) and having an opening (10) located above the substrate portion (2), removing the fill material (4) disposed above the dielectric layer (3), thereby leaving an exposed top surface (6) of the dielectric layer (3) and residual fill material (15) within the opening (10), forming a hard mask material (5) on the exposed top surface (6) of the dielectric layer (3) and on the residual fill material (15), patterning the hard mask material (5) for forming a hard mask (25) having trenches (8a, 8b) extending along a lateral direction (X) and exposing portions of the residual fill material (15) adjacent to the dielectric layer (3) and portions of the dielectric layer (3) adjacent to the residual fill material (15), anisotropically etching the dielectric layer (3), the residual fill material (15) and the substrate (1) selectively to the hard mask (5)

Abstract: A method for selective masking is described. In this case, a filling material is applied to a structure which, as a function of the aspect ratio of the structure, forms cavities when the aspect ratio is high. The filling layer is then removed as far as the cavities and, using an etching process, filling material is removed completely from the recesses in which the cavities are formed. In this way, areas are exposed selectively.

Abstract: In a method for producing a trench transistor, a substrate of a first conduction type is provided and a trench in the substrate and a gate dielectric in the trench are formed. A first conductive filling in the trench as a gate electrode on the gate dielectric and first source and drain regions are formed. An etched-back first conductive filling is produced by etching back the first conductive filling down to a depth below the first source and drain regions and second source and drain regions are formed. The second source and drain regions adjoin the first source and drain regions and extend to a depth at least as far as the etched-back first conductive filling. An insulation spacer above the etched-back first conductive filling is formed in the trench and a second conductive filling is provided in the trench as an upper part of the gate electrode.

Abstract: A method for producing a structure with a low aspect ratio is disclosed. In one embodiment, an initial structure is formed conformally within an opening in a semiconductor substrate, the opening being filled with a sacrificial structure, and the initial structure being removed outside the opening. By removing a part of the initial structure in the sidewall region between the sacrificial structure and the semiconductor substrate, a structure with a low aspect ratio is provided.

Abstract: A description is given of a method for a selective masking of a structure with a small structure surface with respect to a structure with a larger structure surface. To that end, the structures are filled with a covering layer. The covering layer is formed with a larger thickness above the first structure, which has the larger structure surface, than above the second structure. Afterward, the covering layer is removed by a homogeneous removal method, so that first the structure surface of the second structure is uncovered. A simple self-aligning method for fabricating a mask for uncovering the second structure is thus provided.

Abstract: To fabricate a hole trench storage capacitor having an inner electrode, which is formed in a hole trench, and an outer electrode, which is formed in an electrode section, surrounding the hole trench in a lower section, of the semiconductor substrate, the inner electrode is continued above the substrate surface of the semiconductor substrate. Then, an additional layer, which widens the semiconductor substrate, is grown onto the substrate surface by an epitaxy process. A transition surface for contact-connection of the inner electrode and at least a part of an insulation collar is formed above the original substrate surface, thereby increasing the size of a surface area of the hole trench storage capacitor, which can be used for charge storage, while using the same aspect ratio for an etch used to form the hole trench.

Abstract: Process for producing an etching mask on a microstructure, in particular a semiconductor structure with trench capacitors, and corresponding uses of the etching mask which allow for extremely thin photoresist layers to be employed.

Abstract: A method for fabricating a semiconductor structure includes providing a semiconductor substrate, providing a plurality of trenches in the semiconductor substrate using a first hard mask, and causing the hard mask to recede by a predetermined distance with respect to the trench wall at the top side of the semiconductor substrate for forming a first hard mask that has been caused to recede. An isolation trench structure is provided in the semiconductor substrate using a second hard mask, the isolation trench structure subdividing the first first hard mask that has been caused to recede along rows into strip sections and the strip sections of adjacent rows being arranged offset with respect to one another. The receding process results in a reduction of an overlap region between two strip sections of adjacent rows in comparison with an overlap region which would be present without the receding process.

Abstract: A method for selective masking is described. In this case, a filling material is applied to a structure which, as a function of the aspect ratio of the structure, forms cavities when the aspect ratio is high. The filling layer is then removed as far as the cavities and, using an etching process, filling material is removed completely from the recesses in which the cavities are formed. In this way, areas are exposed selectively.

Abstract: A method for etching trenches having different depths on a semiconductor substrate includes providing a mask with first and second openings. The first and second openings are located where corresponding first and second trenches are to be etched. A slow-etch region, made of a slow-etch material, is provided above the substrate at a location corresponding to the second opening. When exposed to a selected etchant, the slow-etch material is etched at a rate less than the rate at which the semiconductor substrate is etched when exposed to the selected etchant.

Abstract: A method for the fabrication of an integrated semiconductor component, in which at least one isolation trench is formed, a first layer of a nonconductive material is applied by a nonconformal deposition method, and a second layer of a nonconductive material is applied by a conformal deposition method at least to the back surface of the semiconductor component.

Abstract: A method for fabricating a trench capacitor with an insulation collar in a substrate, which is electrically connected to the substrate on one side via a buried contact, using a hard mask with a corresponding mask opening.

Abstract: To fabricate a hole trench storage capacitor having an inner electrode, which is formed in a hole trench, and an outer electrode, which is formed in an electrode section, surrounding the hole trench in a lower section, of the semiconductor substrate, the inner electrode is continued above the substrate surface of the semiconductor substrate. Then, an additional layer, which widens the semiconductor substrate, is grown onto the substrate surface by an epitaxy process. A transition surface for contact-connection of the inner electrode and at least a part of an insulation collar is formed above the original substrate surface, thereby increasing the size of a surface area of the hole trench storage capacitor, which can be used for charge storage, while using the same aspect ratio for an etch used to form the hole trench.