Abstract: A micromechanical component for a capacitive pressure sensor device, including a diaphragm that is stretched with the aid of a frame structure in such a way that a cantilevered area of the diaphragm spans a framed partial surface, and including a reinforcement structure that is formed at the cantilevered area. A first spatial direction oriented in parallel to the framed partial surface is definable in which the cantilevered area has a minimal extension, and a second spatial direction oriented in parallel to the framed partial surface and oriented perpendicularly with respect to the first spatial direction is definable in which the cantilevered area has a greater extension. The reinforcement structure is present at a first distance from the frame structure in the first spatial direction, and at a second distance in the second spatial direction, the second distance being greater than the first distance.

Abstract: Disclosed is a method for producing a semiconductor device, the method including forming a plurality of semiconductor arrangements one above the other, wherein forming each of the plurality of semiconductor arrangements includes forming a semiconductor layer, forming a plurality of trenches in a first surface of the semiconductor layer, and implanting dopant atoms of at least one of a first type and a second type into at least one of a first sidewall and a second sidewall of each of the plurality of trenches. Forming of at least one of the plurality of semiconductor arrangements further includes forming a protective layer covering mesa regions between the plurality of trenches of the respective semiconductor layer, and covering a bottom, the first sidewall and the second sidewall of each of the plurality of trenches that are formed in the respective semiconductor layer.

Abstract: The present invention provides novel methods for reducing the serine protease and/or serine protease zymogen content of a plasma-derived protein composition. Also provided are methods for manufacturing plasma-derived protein compositions having reduced serine protease and\or serine protease zymogen content. Among yet other aspects, the present invention provides aqueous and lyophilized compositions of plasma-derived proteins having reduced serine protease and/or serine protease zymogen content. Yet other aspects include methods for treating, managing, and/or preventing a disease comprising the administration of a plasma-derived protein composition having a reduced serine protease or serine protease zymogen content.

Abstract: A compound of formula wherein V, W, X and Y represent N or CH, at least one of V, W, X and Y being N and at least two of V, W, X and Y being CH; R1, R2 and R3 are each independently of the other hydrogen, C1-C8 alkyl, C1-C8 alkoxy, nitro, cyano, trifluoromethyl, halogen or hydroxy; and the compound provides good lightfastness properties to textile fibre materials, in particular PES fibre materials.

Abstract: A micromechanical component for a capacitive pressure sensor device includes a substrate; a frame structure that frames a partial surface; a membrane that is tensioned by the frame structure such that a self-supporting region of the membrane extends over the framed partial surface and an internal volume with a reference pressure therein is sealed in an airtight fashion, the self-supporting region of the membrane being deformable by a physical pressure on an external side of the self-supporting region that not equal to the reference pressure; a measurement electrode situated on the framed partial surface; and a reference measurement electrode that is situated on the framed partial surface and is electrically insulated from the measurement electrode.

Abstract: A sensor device having a first counter electrode extending under an intermediate carrier, and having a first distance between the intermediate carrier and the first counter electrode being modifiable by the pressure on the movable region, and the first counter electrode encompassing, under the intermediate carrier, at least one electrically separated region that is disposed below a spacing element and includes at least a lateral extent of the spacing element.

Abstract: A method and a transistor device are disclosed. The transistor device includes: a semiconductor body; first regions of a first doping type and second regions of a second doping type in an inner region and an edge region of the semiconductor body; transistor cells in the inner region of the semiconductor body, each transistor cell including a body region and a source region, the transistor cells including a common drain region; and a buffer region arranged between the drain region and the first and second regions. A dopant dose in the first and second regions decreases towards an edge surface of the semiconductor body. A dopant dose in the buffer region decreases towards the edge surface.

Abstract: A vertical junction field effect transistor includes mesa regions and trench structures extending along a first lateral direction in a semiconductor body and arranged alternately along a second lateral direction. The trench structures include a gate contact material electrically connected to a gate region of a first conductivity type in the semiconductor body. A width of the trench structures satisfies one or more of the following conditions: i) the width of at least one trench structure arranged outermost along the second lateral direction is smaller than in a more central part of the trench structures; or ii) the width of at least some trench structures is smaller along an end part in the first lateral direction than in the more central part, an extent of the end part along the first lateral direction being larger than a pitch between neighboring trench structures along the second lateral direction.

Abstract: A micromechanical component, whose diaphragm is supported and has support structures on its inner diaphragm side. Each of the support structures includes a first and second edge element structure, and at least one intermediate element structure positioned between the first and second edge element structures. For each of the support structures, a plane of symmetry is definable, with respect to which at least the first edge element structure of the respective support structure and the second edge element structure of the respective support structure are specularly symmetric. In each of support structures, a first maximum dimension of its first edge element structure perpendicular to its plane of symmetry and a second maximum dimension of its second edge element structure perpendicular to its plane of symmetry are greater than the maximum dimension of its intermediate element structure perpendicular to its plane of symmetry.

Abstract: A method of forming a semiconductor device includes providing a base substrate comprising SiC and a growth surface extending along a plane that is angled relative to a first crystallographic plane of the SiC from the base substrate, forming first and second trenches in the base substrate that extend from the growth surface into the base substrate, epitaxially forming a first SiC layer on the growth surface of the base substrate by a step-controlled epitaxy technique, and epitaxially forming a second SiC layer on the first SiC layer, wherein the first SiC layer is a layer of ?-SiC, and wherein the second SiC layer is a layer of ?-SiC.

Abstract: Disclosed is a method for producing a semiconductor device, the method including forming a plurality of semiconductor arrangements one above the other, wherein forming each of the plurality of semiconductor arrangements includes forming a semiconductor layer, forming a plurality of trenches in a first surface of the semiconductor layer, and implanting dopant atoms of at least one of a first type and a second type into at least one of a first sidewall and a second sidewall of each of the plurality of trenches. Forming of at least one of the plurality of semiconductor arrangements further includes forming a protective layer covering mesa regions between the plurality of trenches of the respective semiconductor layer, and covering a bottom, the first sidewall and the second sidewall of each of the plurality of trenches that are formed in the respective semiconductor layer.

Abstract: A method includes forming a trench in a first surface in an edge region of a semiconductor body, forming a plurality of superjunction transistor cells in an inner region of a semiconductor body, and forming an insulation layer on the first surface of the semiconductor body in the edge region and in the inner region, wherein forming the insulation layer includes a thermal oxidation process.

Abstract: A method is disclosed. The method includes switching off a power transistor circuit in an electronic circuit. The electronic circuit includes a power source and a load circuit. The power transistor circuit is connected between the power source and the load circuit. Switching off the power transistor circuit includes operating at least one power transistor included in the power transistor circuit in an Avalanche mode so that at least a portion of energy stored in the electronic circuit before switching off the power transistor circuit is dissipated in the at least one power transistor.

Abstract: A trench junction field effect transistor (trench JFET) includes a mesa region confined by first and second trenches along a first lateral direction. The first and second trenches extend into a semiconductor body from a first surface of the semiconductor body. A mesa channel region of a first conductivity type is confined, along the first lateral direction, by first and second gate regions of a second conductivity type. A first pn junction is defined by the mesa channel region and the first gate region. A second pn junction is defined by the mesa channel region and the second gate region. The mesa channel region includes, along the first lateral direction, first, second and third mesa channel sub-regions having a same extent along the first lateral direction.

Abstract: Electronic circuits are disclosed. One electronic circuit includes: a transistor device having a load path and a drive input; a first drive circuit configured to receive a supply voltage and generate a drive signal for the transistor device based on the supply voltage; and a biasing circuit connected in parallel with the load path of the transistor device. The biasing circuit includes a bias voltage circuit configured to receive the supply voltage and generate a bias voltage higher than the supply voltage based on the supply voltage.

Abstract: A method for forming a semiconductor device includes: forming a trench structure with trenches in an inner region and an edge region of a SiC semiconductor body such that the trench structure extends from a first surface of the semiconductor body through a second semiconductor layer into a first semiconductor layer and such that the trench structure, in the second semiconductor layer, forms mesa regions; and forming at least one transistor cell at least partially in each of the mesa regions in the inner region. Forming each transistor cell includes forming at least one compensation region. Forming the compensation region includes implanting dopant atoms of a second doping type via sidewalls of the trenches into the mesa regions in the inner region. Forming the compensation region in each mesa region in the inner region includes at least partially covering the edge region with an implantation mask.

Abstract: In a method and apparatus for determining an examination duration tolerable by a patient in and/or on a diagnostic examination device, the patient to be examined is observed at least in a preliminary stage of the examination concerned, during which measurement parameters are ascertained. From the measurement parameters, an algorithm determines a statement about the dwell capability of the patient in the examination device. The algorithm can be an artificial neural network.

Abstract: A method for producing a semiconductor device includes forming transistor cells in a semiconductor body, each cell including a drift region separated from a source region by a body region, a gate electrode dielectrically insulated from the body region, and a compensation region of a doping type complementary to the doping type of the drift region and extending from a respective body region into the drift region in a vertical direction. Forming the drift and compensation regions includes performing a first implantation step, thereby implanting first and second type dopant atoms into the semiconductor body, wherein an implantation dose of at least one of the first type dopant atoms and the second type dopant atoms for each of at least two sections of the semiconductor body differs from the implantation dose of the corresponding type of dopant atoms of at least one other section of the at least two sections.

Abstract: A transistor device is disclosed.

Abstract: An electronic circuit is disclosed. The electronic circuit includes: a half-bridge with a first transistor device (1) and a second transistor device (1a); a first biasing circuit (3) connected in parallel with a load path of the first transistor device (1) and comprising a first electronic switch (31); a second biasing circuit (3a) connected in parallel with a load path of the second transistor device (1a) and comprising a second electronic switch (31a); and a drive circuit arrangement (DRVC). The drive circuit arrangement (DRVC) is configured to receive a first half-bridge input signal (Sin) and a second half-bridge input signal (Sina), drive the first transistor device (1) and the second electronic switch (31a) based on the first half-bridge input signal (Sin), and drive the second transistor device (1a) and the first electronic switch (31) based on the second half-bridge input signal (Sina).