Abstract: A method is disclosed. The method includes switching off a power transistor circuit in an electronic circuit. The electronic circuit includes a power source and a load circuit. The power transistor circuit is connected between the power source and the load circuit. Switching off the power transistor circuit includes operating at least one power transistor included in the power transistor circuit in an Avalanche mode so that at least a portion of energy stored in the electronic circuit before switching off the power transistor circuit is dissipated in the at least one power transistor.

Abstract: Disclosed is a transistor device with an edge termination structure and a method. The method includes forming an edge termination structure of a transistor device. Forming the edge termination structure includes: forming an edge trench in an edge region of a semiconductor body such that the edge trench has a trench bottom and an inner trench sidewall facing an inner region of the semiconductor body; and forming a first edge region of a second doping type adjacent to the inner trench sidewall. Forming the first edge region includes implanting dopant atoms of the second doping type at least into the inner trench sidewall.

Abstract: A transistor device is disclosed. The transistor device includes a semiconductor body and plurality of transistor cells. Each transistor cell includes: a drift region and a source region of a first doping type; a body region of a second doping type complementary to the first doping type; a field shaping region of the second doping type connected to a source node; and a gate electrode connected to a gate node. The gate electrode is arranged in a trench extending from a first surface into the semiconductor body. The gate electrode is dielectrically insulated from the body region by a gate dielectric. At least portions of the gate electrode are dielectrically insulated from the drift region by a field dielectric. The field shaping region adjoins the trench. The field dielectric comprises a high-k dielectric.

Abstract: A transistor device and a method for producing source regions of a transistor device are disclosed. The transistor device includes a semiconductor body with a plurality of mesa regions and a plurality of transistor cells each formed in a respective one of the mesa regions. Each transistor cell includes: a source region of a first doping type; a gate region of a second doping type complementary to the first doping type and spaced apart from the source region; a channel region of the first doping type; and a transition region different from the source region and the gate region. The transition region is arranged between the source region and the gate region and adjoins both the source region and the gate region.

Abstract: A transistor device and a method for manufacturing a transistor device are disclosed. The transistor device includes a semiconductor body and a plurality of transistor cells. Each transistor cell includes: a drift region, a body region, and a source region; a gate electrode connected to a gate node; and a field electrode connected to a source node. The gate electrode is dielectrically insulated from the body region by a gate dielectric, and is arranged in a first trench extending from a first surface into the semiconductor body. The field electrode is dielectrically insulated from the drift region by a high-k dielectric, and is arranged in a second trench. The second trench extends from the first surface into the semiconductor body and is spaced apart from the first trench, and the field electrode extends at least as deep as the first trench into the semiconductor body.

Abstract: An electronic circuit is disclosed. The electronic circuit includes: a half-bridge with a first transistor device (1) and a second transistor device (1a); a first biasing circuit (3) connected in parallel with a load path of the first transistor device (1) and comprising a first electronic switch (31); a second biasing circuit (3a) connected in parallel with a load path of the second transistor device (1a) and comprising a second electronic switch (31a); and a drive circuit arrangement (DRVC). The drive circuit arrangement (DRVC) is configured to receive a first half-bridge input signal (Sin) and a second half-bridge input signal (Sina), drive the first transistor device (1) and the second electronic switch (31a) based on the first half-bridge input signal (Sin), and drive the second transistor device (1a) and the first electronic switch (31) based on the second half-bridge input signal (Sina).

Abstract: A local coil for a magnetic resonance apparatus, including: at least one antenna designed to receive radio frequency signals in a frequency and power range of a magnetic resonance measurement; a holding element designed to hold the at least one antenna in a position that is appropriate for application on a diagnostically relevant body region of a patient, wherein the at least one antenna is mechanically connected to the holding element; a base element, wherein a first end of the holding element is mechanically connected to the base element and wherein a second end of the holding element opposite the first end is free-floating; and a guide system that is mechanically connected to the base element and the holding element, and is designed to position the holding element variably with respect to the base element.

Abstract: A superjunction transistor device includes a drift region with a plurality of first regions of a first doping type and a plurality of second regions of a second type in a semiconductor body. The first regions and the second regions are arranged alternately in the semiconductor body. The second regions include wide regions having a first width and narrow regions having a second width. The wide regions and the narrow regions are arranged alternately. The first width is at least 1.05 times the second width.

Abstract: A movement detection method is calibrated for a magnetic resonance apparatus. An examination object is positioned on a movement apparatus. During a training phase, training data is recorded according to the movement detection method, wherein the examination object is simultaneously moved by the movement apparatus. The movement detection method is calibrated on the basis of the training data.

Abstract: A method for forming a drift region of a superjunction transistor and a superjunction transistor device are disclosed. The method includes forming first regions of a first doping type and second regions of a second type in a semiconductor body such that the first and second regions are arranged alternatingly in the body. The first and second regions are formed by: forming trenches in at least one semiconductor layer; implanting first type dopant atoms and second type dopant atoms into opposing sidewalls of the trenches; filling the trenches with a semiconductor material; and diffusing the dopant atoms in a thermal process so that the first type dopant atoms form the first regions and the second type dopant atoms form the second regions. Each trench has a first width, the trenches are separated by mesa regions each having a second width, and the first width is greater than the second width.

Abstract: Disclosed is a method for producing a semiconductor device, the method including forming a plurality of semiconductor arrangements one above the other, wherein forming each of the plurality of semiconductor arrangements includes forming a semiconductor layer, forming a plurality of trenches in a first surface of the semiconductor layer, and implanting dopant atoms of at least one of a first type and a second type into at least one of a first sidewall and a second sidewall of each of the plurality of trenches. Forming of at least one of the plurality of semiconductor arrangements further includes forming a protective layer covering mesa regions between the plurality of trenches of the respective semiconductor layer, and covering a bottom, the first sidewall and the second sidewall of each of the plurality of trenches that are formed in the respective semiconductor layer.

Abstract: A method and a transistor device are disclosed. The transistor device includes: a semiconductor body; first regions of a first doping type and second regions of a second doping type in an inner region and an edge region of the semiconductor body; transistor cells in the inner region of the semiconductor body, each transistor cell including a body region and a source region, the transistor cells including a common drain region; and a buffer region arranged between the drain region and the first and second regions. A dopant dose in the first and second regions decreases towards an edge surface of the semiconductor body. A dopant dose in the buffer region decreases towards the edge surface.

Abstract: A vertical junction field effect transistor includes mesa regions and trench structures extending along a first lateral direction in a semiconductor body and arranged alternately along a second lateral direction. The trench structures include a gate contact material electrically connected to a gate region of a first conductivity type in the semiconductor body. A width of the trench structures satisfies one or more of the following conditions: i) the width of at least one trench structure arranged outermost along the second lateral direction is smaller than in a more central part of the trench structures; or ii) the width of at least some trench structures is smaller along an end part in the first lateral direction than in the more central part, an extent of the end part along the first lateral direction being larger than a pitch between neighboring trench structures along the second lateral direction.

Abstract: A method of forming a semiconductor device includes providing a base substrate comprising SiC and a growth surface extending along a plane that is angled relative to a first crystallographic plane of the SiC from the base substrate, forming first and second trenches in the base substrate that extend from the growth surface into the base substrate, epitaxially forming a first SiC layer on the growth surface of the base substrate by a step-controlled epitaxy technique, and epitaxially forming a second SiC layer on the first SiC layer, wherein the first SiC layer is a layer of ?-SiC, and wherein the second SiC layer is a layer of ?-SiC.

Abstract: Disclosed is a method for producing a semiconductor device, the method including forming a plurality of semiconductor arrangements one above the other, wherein forming each of the plurality of semiconductor arrangements includes forming a semiconductor layer, forming a plurality of trenches in a first surface of the semiconductor layer, and implanting dopant atoms of at least one of a first type and a second type into at least one of a first sidewall and a second sidewall of each of the plurality of trenches. Forming of at least one of the plurality of semiconductor arrangements further includes forming a protective layer covering mesa regions between the plurality of trenches of the respective semiconductor layer, and covering a bottom, the first sidewall and the second sidewall of each of the plurality of trenches that are formed in the respective semiconductor layer.

Abstract: A method includes forming a trench in a first surface in an edge region of a semiconductor body, forming a plurality of superjunction transistor cells in an inner region of a semiconductor body, and forming an insulation layer on the first surface of the semiconductor body in the edge region and in the inner region, wherein forming the insulation layer includes a thermal oxidation process.

Abstract: A method is disclosed. The method includes switching off a power transistor circuit in an electronic circuit. The electronic circuit includes a power source and a load circuit. The power transistor circuit is connected between the power source and the load circuit. Switching off the power transistor circuit includes operating at least one power transistor included in the power transistor circuit in an Avalanche mode so that at least a portion of energy stored in the electronic circuit before switching off the power transistor circuit is dissipated in the at least one power transistor.

Abstract: A trench junction field effect transistor (trench JFET) includes a mesa region confined by first and second trenches along a first lateral direction. The first and second trenches extend into a semiconductor body from a first surface of the semiconductor body. A mesa channel region of a first conductivity type is confined, along the first lateral direction, by first and second gate regions of a second conductivity type. A first pn junction is defined by the mesa channel region and the first gate region. A second pn junction is defined by the mesa channel region and the second gate region. The mesa channel region includes, along the first lateral direction, first, second and third mesa channel sub-regions having a same extent along the first lateral direction.

Abstract: Electronic circuits are disclosed. One electronic circuit includes: a transistor device having a load path and a drive input; a first drive circuit configured to receive a supply voltage and generate a drive signal for the transistor device based on the supply voltage; and a biasing circuit connected in parallel with the load path of the transistor device. The biasing circuit includes a bias voltage circuit configured to receive the supply voltage and generate a bias voltage higher than the supply voltage based on the supply voltage.

Abstract: A method for forming a semiconductor device includes: forming a trench structure with trenches in an inner region and an edge region of a SiC semiconductor body such that the trench structure extends from a first surface of the semiconductor body through a second semiconductor layer into a first semiconductor layer and such that the trench structure, in the second semiconductor layer, forms mesa regions; and forming at least one transistor cell at least partially in each of the mesa regions in the inner region. Forming each transistor cell includes forming at least one compensation region. Forming the compensation region includes implanting dopant atoms of a second doping type via sidewalls of the trenches into the mesa regions in the inner region. Forming the compensation region in each mesa region in the inner region includes at least partially covering the edge region with an implantation mask.