Patents by Inventor Hans Weber

Hans Weber has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11912563
    Abstract: A micromechanical component, whose diaphragm is supported and has support structures on its inner diaphragm side. Each of the support structures includes a first and second edge element structure, and at least one intermediate element structure positioned between the first and second edge element structures. For each of the support structures, a plane of symmetry is definable, with respect to which at least the first edge element structure of the respective support structure and the second edge element structure of the respective support structure are specularly symmetric. In each of support structures, a first maximum dimension of its first edge element structure perpendicular to its plane of symmetry and a second maximum dimension of its second edge element structure perpendicular to its plane of symmetry are greater than the maximum dimension of its intermediate element structure perpendicular to its plane of symmetry.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: February 27, 2024
    Assignee: ROBERT BOSCH GMBH
    Inventors: Hans Artmann, Christoph Hermes, Heribert Weber, Jochen Reinmuth, Peter Schmollngruber, Thomas Friedrich
  • Publication number: 20240047207
    Abstract: A method of forming a semiconductor device includes providing a base substrate comprising SiC and a growth surface extending along a plane that is angled relative to a first crystallographic plane of the SiC from the base substrate, forming first and second trenches in the base substrate that extend from the growth surface into the base substrate, epitaxially forming a first SiC layer on the growth surface of the base substrate by a step-controlled epitaxy technique, and epitaxially forming a second SiC layer on the first SiC layer, wherein the first SiC layer is a layer of ?-SiC, and wherein the second SiC layer is a layer of ?-SiC.
    Type: Application
    Filed: August 2, 2022
    Publication date: February 8, 2024
    Inventors: Christian Zmoelnig, Tobias Franz Wolfgang Hoechbauer, Andreas Voerckel, Hans Weber
  • Patent number: 11894445
    Abstract: Disclosed is a method for producing a semiconductor device, the method including forming a plurality of semiconductor arrangements one above the other, wherein forming each of the plurality of semiconductor arrangements includes forming a semiconductor layer, forming a plurality of trenches in a first surface of the semiconductor layer, and implanting dopant atoms of at least one of a first type and a second type into at least one of a first sidewall and a second sidewall of each of the plurality of trenches. Forming of at least one of the plurality of semiconductor arrangements further includes forming a protective layer covering mesa regions between the plurality of trenches of the respective semiconductor layer, and covering a bottom, the first sidewall and the second sidewall of each of the plurality of trenches that are formed in the respective semiconductor layer.
    Type: Grant
    Filed: August 4, 2021
    Date of Patent: February 6, 2024
    Assignee: Infineon Technologies Austria AG
    Inventors: Daniel Tutuc, Matthias Kuenle, Ingo Muri, Hans Weber
  • Patent number: 11869966
    Abstract: A method includes forming a trench in a first surface in an edge region of a semiconductor body, forming a plurality of superjunction transistor cells in an inner region of a semiconductor body, and forming an insulation layer on the first surface of the semiconductor body in the edge region and in the inner region, wherein forming the insulation layer includes a thermal oxidation process.
    Type: Grant
    Filed: November 17, 2021
    Date of Patent: January 9, 2024
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans Weber, Christian Fachmann, Franz Hirler, Winfried Kaindl, Markus Rochel
  • Publication number: 20230344422
    Abstract: A method is disclosed. The method includes switching off a power transistor circuit in an electronic circuit. The electronic circuit includes a power source and a load circuit. The power transistor circuit is connected between the power source and the load circuit. Switching off the power transistor circuit includes operating at least one power transistor included in the power transistor circuit in an Avalanche mode so that at least a portion of energy stored in the electronic circuit before switching off the power transistor circuit is dissipated in the at least one power transistor.
    Type: Application
    Filed: April 4, 2023
    Publication date: October 26, 2023
    Inventors: Christian Fachmann, Matteo-Alessandro Kutschak, Otto Wiedenbauer, Winfried Kaindl, Hans Weber
  • Publication number: 20230261117
    Abstract: A trench junction field effect transistor (trench JFET) includes a mesa region confined by first and second trenches along a first lateral direction. The first and second trenches extend into a semiconductor body from a first surface of the semiconductor body. A mesa channel region of a first conductivity type is confined, along the first lateral direction, by first and second gate regions of a second conductivity type. A first pn junction is defined by the mesa channel region and the first gate region. A second pn junction is defined by the mesa channel region and the second gate region. The mesa channel region includes, along the first lateral direction, first, second and third mesa channel sub-regions having a same extent along the first lateral direction.
    Type: Application
    Filed: February 7, 2023
    Publication date: August 17, 2023
    Inventors: Hans Weber, David Kammerlander, Andreas Riegler
  • Patent number: 11728790
    Abstract: Electronic circuits are disclosed. One electronic circuit includes: a transistor device having a load path and a drive input; a first drive circuit configured to receive a supply voltage and generate a drive signal for the transistor device based on the supply voltage; and a biasing circuit connected in parallel with the load path of the transistor device. The biasing circuit includes a bias voltage circuit configured to receive the supply voltage and generate a bias voltage higher than the supply voltage based on the supply voltage.
    Type: Grant
    Filed: April 4, 2022
    Date of Patent: August 15, 2023
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans Weber, Franz Hirler, Matteo-Alessandro Kutschak, Andreas Riegler
  • Publication number: 20230238427
    Abstract: A method for forming a semiconductor device includes: forming a trench structure with trenches in an inner region and an edge region of a SiC semiconductor body such that the trench structure extends from a first surface of the semiconductor body through a second semiconductor layer into a first semiconductor layer and such that the trench structure, in the second semiconductor layer, forms mesa regions; and forming at least one transistor cell at least partially in each of the mesa regions in the inner region. Forming each transistor cell includes forming at least one compensation region. Forming the compensation region includes implanting dopant atoms of a second doping type via sidewalls of the trenches into the mesa regions in the inner region. Forming the compensation region in each mesa region in the inner region includes at least partially covering the edge region with an implantation mask.
    Type: Application
    Filed: January 23, 2023
    Publication date: July 27, 2023
    Inventor: Hans Weber
  • Patent number: 11647918
    Abstract: In a method and apparatus for determining an examination duration tolerable by a patient in and/or on a diagnostic examination device, the patient to be examined is observed at least in a preliminary stage of the examination concerned, during which measurement parameters are ascertained. From the measurement parameters, an algorithm determines a statement about the dwell capability of the patient in the examination device. The algorithm can be an artificial neural network.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: May 16, 2023
    Inventors: David Grodzki, Hans Weber
  • Patent number: 11652138
    Abstract: A method for producing a semiconductor device includes forming transistor cells in a semiconductor body, each cell including a drift region separated from a source region by a body region, a gate electrode dielectrically insulated from the body region, and a compensation region of a doping type complementary to the doping type of the drift region and extending from a respective body region into the drift region in a vertical direction. Forming the drift and compensation regions includes performing a first implantation step, thereby implanting first and second type dopant atoms into the semiconductor body, wherein an implantation dose of at least one of the first type dopant atoms and the second type dopant atoms for each of at least two sections of the semiconductor body differs from the implantation dose of the corresponding type of dopant atoms of at least one other section of the at least two sections.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: May 16, 2023
    Assignee: Infineon Technologies Austria AG
    Inventors: Ingo Muri, Felix Schubert, Daniel Tutuc, Hans Weber
  • Publication number: 20230126534
    Abstract: A transistor device is disclosed.
    Type: Application
    Filed: January 19, 2021
    Publication date: April 27, 2023
    Inventors: Hans Weber, Björn Fischer, Franz Hirler, Matteo-Alessandro Kutschak, Andreas Riegler
  • Publication number: 20230075897
    Abstract: An electronic circuit is disclosed. The electronic circuit includes: a half-bridge with a first transistor device (1) and a second transistor device (1a); a first biasing circuit (3) connected in parallel with a load path of the first transistor device (1) and comprising a first electronic switch (31); a second biasing circuit (3a) connected in parallel with a load path of the second transistor device (1a) and comprising a second electronic switch (31a); and a drive circuit arrangement (DRVC). The drive circuit arrangement (DRVC) is configured to receive a first half-bridge input signal (Sin) and a second half-bridge input signal (Sina), drive the first transistor device (1) and the second electronic switch (31a) based on the first half-bridge input signal (Sin), and drive the second transistor device (1a) and the first electronic switch (31) based on the second half-bridge input signal (Sina).
    Type: Application
    Filed: March 5, 2021
    Publication date: March 9, 2023
    Inventors: Hans Weber, Franz Hirler, Matteo-Alessandro Kutschak, Manfred Pippan, Andreas Riegler
  • Patent number: 11585877
    Abstract: The disclosure relates to a magnetic resonance apparatus with a patient positioning apparatus comprising at least one coil plug-in element and a communication unit, wherein the magnetic resonance apparatus comprises an adapter apparatus with a communication interface and the adapter apparatus is adapted to couple the communication unit to the at least one coil plug-in element of the patient positioning apparatus.
    Type: Grant
    Filed: September 8, 2021
    Date of Patent: February 21, 2023
    Assignee: Siemens Healthcare GmbH
    Inventor: Hans Weber
  • Publication number: 20230051830
    Abstract: A transistor device and a method for forming a transistor device are disclosed. The transistor device includes: a SiC semiconductor body that includes a first semiconductor layer and a second semiconductor layer formed on top of the first semiconductor; a trench structure extending from a first surface of the semiconductor body through the second semiconductor layer into the first semiconductor layer; a drain region arranged in the first semiconductor layer; and a plurality of transistor cells each coupled between the drain region and a source node. The trench structure subdivides the second semiconductor layer into a plurality of mesa regions and includes at least one cavity. At least one of the plurality of transistor cells is at least partially integrated in each of the mesa regions.
    Type: Application
    Filed: August 12, 2022
    Publication date: February 16, 2023
    Inventors: Andreas Voerckel, Hans Weber, Tobias Franz Wolfgang Hoechbauer
  • Patent number: 11527468
    Abstract: A connection body which comprises a base structure at least predominantly made of a semiconductor oxide material or glass material, and an electrically conductive wiring structure on and/or in the base structure, wherein the electrically conductive wiring structure comprises at least one vertical wiring section with a first lateral dimension on and/or in the base structure and at least one lateral wiring section connected with the at least one vertical wiring section, wherein the at least one lateral wiring section has a second lateral dimension on and/or in the base structure, which is different to the first lateral dimension.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: December 13, 2022
    Assignee: Infineon Technologies AG
    Inventors: Andreas Riegler, Christian Fachmann, Matteo-Alessandro Kutschak, Carsten von Koblinski, Hans Weber
  • Patent number: 11508841
    Abstract: A semiconductor device includes a semiconductor body having a first surface and second surface opposite to the first surface in a vertical direction, and a plurality of transistor cells at least partly integrated in the semiconductor body. Each transistor cell includes at least two source regions, first and second gate electrodes spaced apart from each other in a first horizontal direction and arranged adjacent to and dielectrically insulated from a continuous body region, a drift region separated from the at least two source regions by the body region, and at least three contact plugs extending from the body region towards a source electrode in the vertical direction. The at least three contact plugs are arranged successively between the first and second gate electrodes. Only the two outermost contact plugs that are arranged closest to the first and second gate electrodes, respectively, directly adjoin at least one of the source regions.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: November 22, 2022
    Assignee: Infineon Technologies Dresden GmbH & Co. KG
    Inventors: Franz Hirler, Christian Fachmann, Winfried Kaindl, Hans Weber
  • Publication number: 20220310838
    Abstract: A semiconductor device is proposed. An example of the semiconductor device includes a semiconductor body having a first main surface. A trench structure extends into the semiconductor body from the first main surface. The trench structure includes a trench electrode structure and a trench dielectric structure. The trench dielectric structure includes a gate dielectric in an upper part of the trench dielectric structure and a gap in a lower part of the trench dielectric structure. The semiconductor device further includes a body region adjoining the gate dielectric at a sidewall of the trench structure in the upper part of the trench dielectric structure. The gate dielectric extends deeper into the semiconductor body along the sidewall than the body region.
    Type: Application
    Filed: March 15, 2022
    Publication date: September 29, 2022
    Inventors: Hans Weber, David Kammerlander, Andreas Riegler
  • Publication number: 20220270933
    Abstract: A transistor device and a method for forming a transistor device are disclosed. The transistor device includes: first regions of a first doping type and second regions of a second doping type in an inner region and an edge region of a semiconductor body; and transistor cells each having a body region and a source region in the inner region of the semiconductor body. An effective lateral doping dose of the first regions in the edge region is lower than an effective lateral doping dose of the first regions in the inner region. An effective lateral doping dose of the second regions in the edge region is lower than an effective lateral doping dose of the second regions in the inner region.
    Type: Application
    Filed: May 13, 2022
    Publication date: August 25, 2022
    Inventors: Hans Weber, Ingo Muri, Daniel Tutuc
  • Publication number: 20220231671
    Abstract: Electronic circuits are disclosed. One electronic circuit includes: a transistor device having a load path and a drive input; a first drive circuit configured to receive a supply voltage and generate a drive signal for the transistor device based on the supply voltage; and a biasing circuit connected in parallel with the load path of the transistor device. The biasing circuit includes a bias voltage circuit configured to receive the supply voltage and generate a bias voltage higher than the supply voltage based on the supply voltage.
    Type: Application
    Filed: April 4, 2022
    Publication date: July 21, 2022
    Inventors: Hans Weber, Franz Hirler, Matteo-Alessandro Kutschak, Andreas Riegler
  • Patent number: 11348838
    Abstract: A transistor device and a method for forming a transistor device are disclosed. The method includes: forming first regions of a first doping type and second regions of a second doping type in inner and edge regions of a semiconductor body; and forming body and source regions of transistor cells in the inner region. Forming the first and second regions includes: forming first and second implanted regions in the inner and edge regions, each first implanted region including at least dopant atoms of a first doping type and each second implanted region including at least dopant atoms of a second doping type; and diffusing the dopant atoms of both doping types in a thermal process such that dopant atoms of at least one of the first and second doping types have at least one of different diffusion rates and diffusion lengths in the inner and edge regions.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: May 31, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans Weber, Ingo Muri, Daniel Tutuc