Patents by Inventor Hans Weber

Hans Weber has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220002147
    Abstract: A method for sealing entries in a MEMS element. The method includes: providing a functional layer having a functional region; producing a cavity underneath the functional region of the functional layer with the aid of a first entry outside of the functional region of the functional layer; sealing the first entry; producing a second entry to the cavity outside of the functional region of the functional layer; melting sealing material in the region of the second entry; and cooling off the melted sealing material to seal the second entry.
    Type: Application
    Filed: December 13, 2019
    Publication date: January 6, 2022
    Applicant: Robert Bosch GmbH
    Inventors: Christoph Hermes, Hans Artmann, Heribert Weber, Peter Schmollngruber, Thomas Friedrich, Tobias Joachim Menold, Mawuli Ametowobla
  • Publication number: 20220003621
    Abstract: A micromechanical component for a capacitive pressure sensor device, including a diaphragm that is stretched with the aid of a frame structure in such a way that a cantilevered area of the diaphragm spans a framed partial surface, and including a reinforcement structure that is formed at the cantilevered area. A first spatial direction oriented in parallel to the framed partial surface is definable in which the cantilevered area has a minimal extension, and a second spatial direction oriented in parallel to the framed partial surface and oriented perpendicularly with respect to the first spatial direction is definable in which the cantilevered area has a greater extension. The reinforcement structure is present at a first distance from the frame structure in the first spatial direction, and at a second distance in the second spatial direction, the second distance being greater than the first distance.
    Type: Application
    Filed: December 18, 2019
    Publication date: January 6, 2022
    Inventors: Thomas Friedrich, Christoph Hermes, Hans Artmann, Heribert Weber, Peter Schmollngruber, Volkmar Senz
  • Patent number: 11211483
    Abstract: A method and a transistor device are disclosed. The method includes: forming a trench in a first surface in an edge region of a semiconductor body; forming an insulation layer in the trench and on the first surface of the semiconductor body; and planarizing the insulation layer so that a trench insulation layer that fills the trench remains, wherein forming the insulation layer comprises a thermal oxidation process.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: December 28, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans Weber, Christian Fachmann, Franz Hirler, Winfried Kaindl, Markus Rochel
  • Publication number: 20210395074
    Abstract: A micromechanical component, whose diaphragm is supported and has support structures on its inner diaphragm side. Each of the support structures includes a first and second edge element structure, and at least one intermediate element structure positioned between the first and second edge element structures. For each of the support structures, a plane of symmetry is definable, with respect to which at least the first edge element structure of the respective support structure and the second edge element structure of the respective support structure are specularly symmetric. In each of support structures, a first maximum dimension of its first edge element structure perpendicular to its plane of symmetry and a second maximum dimension of its second edge element structure perpendicular to its plane of symmetry are greater than the maximum dimension of its intermediate element structure perpendicular to its plane of symmetry.
    Type: Application
    Filed: December 13, 2019
    Publication date: December 23, 2021
    Inventors: Hans Artmann, Christoph Hermes, Heribert Weber, Jochen Reinmuth, Peter Schmollngruber, Thomas Friedrich
  • Publication number: 20210376063
    Abstract: A method for forming a drift region of a superjunction transistor and a superjunction transistor device are disclosed. The method includes forming first regions of a first doping type and second regions of a second type in a semiconductor body such that the first and second regions are arranged alternatingly in the body. The first and second regions are formed by: forming trenches in at least one semiconductor layer; implanting first type dopant atoms and second type dopant atoms into opposing sidewalls of the trenches; filling the trenches with a semiconductor material; and diffusing the dopant atoms in a thermal process so that the first type dopant atoms form the first regions and the second type dopant atoms form the second regions. Each trench has a first width, the trenches are separated by mesa regions each having a second width, and the first width is greater than the second width.
    Type: Application
    Filed: May 26, 2021
    Publication date: December 2, 2021
    Inventors: Hans Weber, Ingo Muri, Daniel Tutuc
  • Publication number: 20210376064
    Abstract: A method for producing a semiconductor device includes forming transistor cells in a semiconductor body, each cell including a drift region separated from a source region by a body region, a gate electrode dielectrically insulated from the body region, and a compensation region of a doping type complementary to the doping type of the drift region and extending from a respective body region into the drift region in a vertical direction. Forming the drift and compensation regions includes performing a first implantation step, thereby implanting first and second type dopant atoms into the semiconductor body, wherein an implantation dose of at least one of the first type dopant atoms and the second type dopant atoms for each of at least two sections of the semiconductor body differs from the implantation dose of the corresponding type of dopant atoms of at least one other section of the at least two sections.
    Type: Application
    Filed: May 26, 2021
    Publication date: December 2, 2021
    Inventors: Ingo Muri, Felix Schubert, Daniel Tutuc, Hans Weber
  • Patent number: 11189690
    Abstract: A method and a transistor device are disclosed. The method includes: forming first regions of a first doping type and second regions of a second doping type in an inner region and an edge region of a semiconductor body; and forming body regions and source regions of transistor cells in the inner region of the semiconductor body. Forming the first regions and second regions includes: forming semiconductor layers one on top of the other; and in each of the semiconductor layers and before forming a respective next one of the semiconductor layers, forming trenches in the inner region and the edge region and implanting dopant atoms into a first sidewall and a second sidewall of each trench. Implanting the dopant atoms into at least one of the semiconductor layers includes partly covering the trenches in the edge region during an implantation process.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: November 30, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans Weber, Ingo Muri, Maximilian Treiber, Daniel Tutuc
  • Patent number: 11158705
    Abstract: A method includes forming active regions of plurality of transistor cells in an inner region of a semiconductor body, each transistor cell includes a drift region of a first doping type and a compensation region of a second doping type, and forming a field stop region in an edge region of the semiconductor body. Forming the drift and compensation regions includes: forming a plurality of semiconductor layers; in each of the semiconductor layers, before forming a next layer, forming a plurality of first trenches and implanting dopant atoms of the first and/or second doping type into sidewalls of the plurality of first trenches. Forming the field stop region includes: in each semiconductor layer of a selection of the plurality of semiconductor layers, forming at least one second trench and implanting first and/or second type dopant atoms at least into one surface of the at least one second trench.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: October 26, 2021
    Assignee: Infineon Technologies Austria AG
    Inventor: Hans Weber
  • Patent number: 11088275
    Abstract: A method for operating a superjunction transistor device and a transistor arrangement are disclosed. The method includes operating the superjunction transistor device in a diode state. Operating the superjunction transistor device in the diode state includes applying a bias voltage different from zero between a drift region of at least one transistor cell of the superjunction transistor device and a compensation region of a doping type complementary to a doping type of the drift region. The compensation region adjoins the drift region, and a polarity of the bias voltage is such that a pn-junction between the drift region and the compensation region is reverse biased.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: August 10, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans Weber, Christian Fachmann, Franz Hirler, Matteo-Alessandro Kutschak, Andreas Riegler
  • Patent number: 11051763
    Abstract: In a method and medical imaging apparatus for determining a feature characterizing intentional breath-holding by an examination object for acquiring medical raw data with breath-holding algorithm, an algorithm, the algorithm being designed to allocate at least one feature characterizing intentional breath-holding to at least one physiological property. The algorithm includes or accesses trained artificial neural network. A physiological property of the examination object is detected during free breathing of the examination object. The feature characterizing intentional breath-holding by the examination object is determined by the computer, by executing the algorithm with the detected physiological property of the examination object, as an input to the algorithm.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: July 6, 2021
    Assignee: Siemens Healthcare GmbH
    Inventors: David Grodzki, Hans Weber
  • Patent number: 10950487
    Abstract: Disclosed is a method. The method includes forming a trench structure with at least one first trench in a first section of a semiconductor body; forming a second trench that is wider than the first trench in a second section of the semiconductor body; and forming a semiconductor layer on a surface of the semiconductor body in the first section and the second section and in the at least one first trench and the second trench such that the semiconductor layer has a substantially planar surface above the first section and a residual trench remains above the second section. Forming the semiconductor layer includes forming a first epitaxial layer in a first epitaxial growth process and a second epitaxial layer on top of the first epitaxial layer in a second epitaxial growth process.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: March 16, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Daniel Tutuc, Hans Weber
  • Publication number: 20210057576
    Abstract: A transistor device is enclosed. The transistor device includes: a semiconductor body; a plurality of drift regions of a first doping type; a plurality of compensation regions of a second doping type adjoining the drift regions; and a plurality of transistor cells each including a body region adjoining a respective one of the plurality of drift regions, a source region adjoining the body region, and a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric. The source regions of the plurality of transistor cells are connected to a source node, the body regions of the plurality of transistor cells are separated from the plurality of compensation regions in the semiconductor body, and the plurality of compensation regions are ohmically connected to the source node.
    Type: Application
    Filed: August 20, 2020
    Publication date: February 25, 2021
    Inventors: Hans Weber, Björn Fischer, Franz Hirler, Matteo-Alessandro Kutschak, Andreas Riegler
  • Patent number: 10923432
    Abstract: A semiconductor wafer includes an alignment mark contained within in a kerf region of the semiconductor wafer. The alignment mark includes a groove vertically extending from a main surface of the semiconductor wafer to a bottom surface of the groove, and at least one tin protruding from the bottom surface of the groove. The groove has a rectangular shape with four sidewalls and four inside corners, with each of the four inside corners facing the at least one fin. A minimum distance between the at least one fin and a nearest one of the four inside corners is at least 25 ?m.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: February 16, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Andreas Moser, Hans Weber, Johannes Baumgartl, Gabor Mezoesi, Michael Treu
  • Patent number: 10879350
    Abstract: A method for forming a transistor device includes: implanting dopant atoms of a first doping type and dopant atoms of a second doping type into opposite sidewalls of each of a plurality of trenches of a first semiconductor layer having a basic doping of the first doping type, the dopant atoms of the first doping type having a smaller diffusion coefficient than the dopant atoms of the second doping type; filling each trench with a second semiconductor layer of the first doping type; and diffusing the dopant atoms of the first doping type and the dopant atoms of the second doping type such that a plurality of first regions of the first doping type and a plurality of second regions of the second doping type are formed. The second regions are spaced apart from each other. Each first region is at least partially arranged within a respective second region.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: December 29, 2020
    Assignee: Infineon Technologies Austria AG
    Inventor: Hans Weber
  • Publication number: 20200395252
    Abstract: A transistor device and a method for forming a transistor device are disclosed. The method includes: forming first regions of a first doping type and second regions of a second doping type in inner and edge regions of a semiconductor body; and forming body and source regions of transistor cells in the inner region. Forming the first and second regions includes: forming first and second implanted regions in the inner and edge regions, each first implanted region including at least dopant atoms of a first doping type and each second implanted region including at least dopant atoms of a second doping type; and diffusing the dopant atoms of both doping types in a thermal process such that dopant atoms of at least one of the first and second doping types have at least one of different diffusion rates and diffusion lengths in the inner and edge regions.
    Type: Application
    Filed: June 12, 2020
    Publication date: December 17, 2020
    Inventors: Hans Weber, Ingo Muri, Daniel Tutuc
  • Publication number: 20200388703
    Abstract: A semiconductor device includes a semiconductor body having a first surface and second surface opposite to the first surface in a vertical direction, and a plurality of transistor cells at least partly integrated in the semiconductor body. Each transistor cell includes at least two source regions, first and second gate electrodes spaced apart from each other in a first horizontal direction and arranged adjacent to and dielectrically insulated from a continuous body region, a drift region separated from the at least two source regions by the body region, and at least three contact plugs extending from the body region towards a source electrode in the vertical direction. The at least three contact plugs are arranged successively between the first and second gate electrodes. Only the two outermost contact plugs that are arranged closest to the first and second gate electrodes, respectively, directly adjoin at least one of the source regions.
    Type: Application
    Filed: June 4, 2020
    Publication date: December 10, 2020
    Inventors: Franz Hirler, Christian Fachmann, Winfried Kaindl, Hans Weber
  • Patent number: 10811529
    Abstract: A transistor device comprises at least one gate electrode, a gate runner connected to the at least one gate electrode and arranged on top of a semiconductor body, a plurality of gate pads arranged on top of the semiconductor body, and a plurality of resistor arrangements. Each gate pad is electrically connected to the gate runner via a respective one of the plurality of resistor arrangements, and each of the resistor arrangements has an electrical resistance, wherein the resistances of the plurality of resistor arrangements are different.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: October 20, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Andreas Riegler, Christian Fachmann, Bjoern Fischer, Franz Hirler, Gabor Mezoesi, Hans Weber
  • Publication number: 20200287535
    Abstract: A method for operating a superjunction transistor device and a transistor arrangement are disclosed. The method includes operating the superjunction transistor device in a diode state. Operating the superjunction transistor device in the diode state includes applying a bias voltage different from zero between a drift region of at least one transistor cell of the superjunction transistor device and a compensation region of a doping type complementary to a doping type of the drift region. The compensation region adjoins the drift region, and a polarity of the bias voltage is such that a pn-junction between the drift region and the compensation region is reverse biased.
    Type: Application
    Filed: March 6, 2020
    Publication date: September 10, 2020
    Inventors: Hans Weber, Christian Fachmann, Franz Hirler, Matteo-Alessandro Kutschak, Andreas Riegler
  • Patent number: 10770541
    Abstract: A semiconductor device of an embodiment includes transistor cells in a transistor cell area of a semiconductor body. A super junction structure in the semiconductor body includes a plurality of drift sub-regions and compensation sub-regions of opposite first and second conductivity types, respectively, and alternately arranged along a lateral direction. A termination area outside the transistor cell area between an edge of the semiconductor body and the transistor cell area includes first and third termination sub-regions of the first conductivity type, respectively. A second termination sub-region of the second conductivity type is sandwiched between the first and the third termination sub-regions along a vertical direction perpendicular to a first surface of the semiconductor body.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: September 8, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Franz Hirler, Hans Weber
  • Publication number: 20200243340
    Abstract: Forming a semiconductor arrangement includes providing a first semiconductor layer having a first surface, forming a first plurality of trenches in the first surface of the first semiconductor layer, each of the trenches in the first plurality having first and second sidewalls that extend from the first surface to a bottom of the respective trench, implanting first type dopant atoms into the first and second sidewalls of each of the trenches in the first plurality, implanting second type dopant atoms into the first and second sidewalls of each of the trenches in the first plurality, and annealing the semiconductor arrangement to simultaneously activate the first type dopant atoms and the second type dopant atoms.
    Type: Application
    Filed: April 16, 2020
    Publication date: July 30, 2020
    Inventors: Anton Mauder, Hans Weber, Franz Hirler, Johannes Georg Laven, Hans-Joachim Schulze, Werner Schustereder, Maximilian Treiber, Daniel Tutuc, Andreas Voerckel