Abstract: A connection body which comprises a base structure at least predominantly made of a semiconductor oxide material or glass material, and an electrically conductive wiring structure on and/or in the base structure, wherein the electrically conductive wiring structure comprises at least one vertical wiring section with a first lateral dimension on and/or in the base structure and at least one lateral wiring section connected with the at least one vertical wiring section, wherein the at least one lateral wiring section has a second lateral dimension on and/or in the base structure, which is different to the first lateral dimension.

Abstract: A method includes forming first regions of a first doping type and second regions of a second doping type in first and second semiconductor layers such that the first and second regions are arranged alternately in at least one horizontal direction of the first and second semiconductor layers, and forming a control structure with transistor cells each including at least one body region, at least one source region and at least one gate electrode in the second semiconductor layer. Forming the first and second regions includes: forming trenches in the first semiconductor layer and implanting at least one of first and second type dopant atoms into sidewalls of the trenches; forming the second semiconductor layer on the first semiconductor layer such that the second layer fills the trenches; implanting at least one of first and second type dopant atoms into the second semiconductor layer; and at least one temperature process.

Abstract: A method of producing a semiconductor device includes providing a semiconductor body including a semiconductor body material having a dopant diffusion coefficient that is smaller than the corresponding dopant diffusion coefficient of silicon. At least one first semiconductor region doped with dopants of a first conductivity type is produced in the semiconductor body, including by applying a first implantation of first implantation ions. At least one second semiconductor region adjacent to the at least one first semiconductor region and doped with dopants of a second conductivity type complementary to the first conductivity type is produced in the semiconductor body, including by applying a second implantation of second implantation ions.

Abstract: In a method and apparatus for determining an examination duration tolerable by a patient in and/or on a diagnostic examination device, the patient to be examined is observed at least in a preliminary stage of the examination concerned, during which measurement parameters are ascertained. From the measurement parameters, an algorithm determines a statement about the dwell capability of the patient in the examination device. The algorithm can be an artificial neural network.

Abstract: In a method and medical imaging apparatus for determining a feature characterizing intentional breath-holding by an examination object for acquiring medical raw data with breath-holding algorithm, an algorithm, the algorithm being designed to allocate at least one feature characterizing intentional breath-holding to at least one physiological property. The algorithm includes or accesses trained artificial neural network. A physiological property of the examination object is detected during free breathing of the examination object. The feature characterizing intentional breath-holding by the examination object is determined by the computer, by executing the algorithm with the detected physiological property of the examination object, as an input to the algorithm.

Abstract: A transistor device comprises at least one gate electrode, a gate runner connected to the at least one gate electrode and arranged on top of a semiconductor body, a plurality of gate pads arranged on top of the semiconductor body, and a plurality of resistor arrangements. Each gate pad is electrically connected to the gate runner via a respective one of the plurality of resistor arrangements, and each of the resistor arrangements has an electrical resistance, wherein the resistances of the plurality of resistor arrangements are different.

Abstract: A method for forming a transistor device includes: implanting dopant atoms of a first doping type and dopant atoms of a second doping type into opposite sidewalls of each of a plurality of trenches of a first semiconductor layer having a basic doping of the first doping type, the dopant atoms of the first doping type having a smaller diffusion coefficient than the dopant atoms of the second doping type; filling each trench with a second semiconductor layer of the first doping type; and diffusing the dopant atoms of the first doping type and the dopant atoms of the second doping type such that a plurality of first regions of the first doping type and a plurality of second regions of the second doping type are formed. The second regions are spaced apart from each other. Each first region is at least partially arranged within a respective second region.

Abstract: A semiconductor device includes an electrically conductive lead frame which includes a die pad and a plurality of electrically conductive leads, each of the leads in the plurality being spaced apart from the die pad. The semiconductor device further includes first and second integrated switching devices mounted on the die pad, each of the first and second integrated switching devices include electrically conductive gate, source and drain terminals. The source terminal of the first integrated switching device is disposed on a rear surface of the first integrated switching device that faces and electrically connects with the die pad. The drain terminal of the second integrated switching device is disposed on a rear surface of the second integrated switching device that faces and electrically connects with the die pad.

Abstract: A semiconductor device of an embodiment includes transistor cells in a transistor cell area of a semiconductor body. A super junction structure in the semiconductor body includes a plurality of drift sub-regions and compensation sub-regions of opposite first and second conductivity types, respectively, and alternately arranged along a lateral direction. A termination area outside the transistor cell area between an edge of the semiconductor body and the transistor cell area includes first and third termination sub-regions of the first conductivity type, respectively. A second termination sub-region of the second conductivity type is sandwiched between the first and the third termination sub-regions along a vertical direction perpendicular to a first surface of the semiconductor body.

Abstract: A method for providing at least one measurement by a magnetic resonance imaging (MRI) system of a tissue property or underlying tissue property in a region sufficiently close to a metal object, so that the metal object induces artifacts is provided. At least one magnetic resonance imaging signal from the region is acquired through the MRI system. The acquired at least one MRI signal is processed to correct for artifacts induced by the metal object. At least one tissue property or underlying tissue property measurement is extracted from the processed at least one MRI signal.

Abstract: A semiconductor device includes a semiconductor body having first and second opposite sides, a drift region, a body layer at the second side, and a field-stop region in Ohmic connection with the body layer. A source metallization at the second side is in Ohmic connection with the body layer. A drain metallization at the first side is in Ohmic connection with the drift region. A gate electrode at the second side is electrically insulated from the semiconductor body to define an operable switchable channel region in the body layer. A through contact structure extends at least between the first and second sides, and includes a conductive region in Ohmic connection with the gate electrode and a dielectric layer. In a normal projection onto a horizontal plane substantially parallel to the first side, the field-stop region surrounds at least one of the drift region and the gate electrode.

Abstract: An alignment mark in a process surface of a semiconductor layer includes a groove with a minimum width of at least 100 ?m and a vertical extension in a range 100 nm to 1 ?m. The alignment mark further includes at least one fin within the groove at a distance of at least 60 ?m to a closest one of inner corners of the groove.

Abstract: A semiconductor device of an embodiment includes transistor cells in a transistor cell area of a semiconductor body. A super junction structure in the semiconductor body includes a plurality of drift sub-regions and compensation sub-regions of opposite first and second conductivity types, respectively, and alternately arranged along a lateral direction. A termination area outside the transistor cell area between an edge of the semiconductor body and the transistor cell area includes first and third termination sub-regions of the first conductivity type, respectively. A second termination sub-region of the second conductivity type is sandwiched between the first and the third termination sub-regions along a vertical direction perpendicular to a first surface of the semiconductor body.

Abstract: A method of manufacturing semiconductor devices in a semiconductor wafer comprises forming charge compensation device structures in the semiconductor wafer. An electric characteristic related to the charge compensation device structures is measured. At least one of proton irradiation and annealing parameters are adjusted based on the measured electric characteristic. The semiconductor wafer is irradiated with protons and annealed based on the at least one of the adjusted proton irradiation and annealing parameters. Laser beam irradiation parameters are adjusted with respect to different positions on the semiconductor wafer based on the measured electric characteristic. The semiconductor wafer is irradiated with a photon beam at the different positions on the wafer based on the photon beam irradiation parameters.

Abstract: An alignment mark in a process surface of a semiconductor layer includes a groove with a minimum width of at least 100 ?m and a vertical extension in a range 100 nm to 1 ?m. The alignment mark further includes at least one fin within the groove at a distance of at least 60 ?m to a closest one of inner corners of the groove.

Abstract: According to an embodiment of a semiconductor substrate, the semiconductor substrate includes a superjunction structure in a device region of a semiconductor layer and an alignment mark in a kerf region of the semiconductor layer. The superjunction structure includes first regions and second regions of opposite conductivity types, the first and the second regions alternating along at least one horizontal direction. The alignment mark includes a vertical step formed by an alignment structure projecting or recessed from a main surface of the semiconductor layer. The alignment structure is of a material of the first regions of the superjunction structure.

Abstract: A method includes forming first regions of a first doping type and second regions of a second doping type in first and second semiconductor layers such that the first and second regions are arranged alternately in at least one horizontal direction of the first and second semiconductor layers, and forming a control structure with transistor cells each including at least one body region, at least one source region and at least one gate electrode in the second semiconductor layer. Forming the first and second regions includes: forming trenches in the first semiconductor layer and implanting at least one of first and second type dopant atoms into sidewalls of the trenches; forming the second semiconductor layer on the first semiconductor layer such that the second layer fills the trenches; implanting at least one of first and second type dopant atoms into the second semiconductor layer; and at least one temperature process.

Abstract: According to an embodiment of a method of forming a semiconductor device, a semiconductor layer including a first dopant species of a first conductivity type and a second dopant species of a second conductivity type different from the first conductivity type is formed. The semiconductor layer is part of a semiconductor body having opposite first and second surfaces. Trenches are formed in the semiconductor layer at the first surface. The trenches are filled with a filling material including at least a semiconductor material. A thermal oxide is formed at one or both of the first and second surfaces, the thermal oxide having a thickness of at least 200 nm. Thermal processing of the semiconductor body causes diffusion of the first and second dopants species into the filling material.

Abstract: Disclosed is a method that includes forming a plurality of semiconductor arrangements one above the other. In this method, forming each of the plurality of semiconductor arrangements includes: forming a semiconductor layer; forming a plurality of trenches in a first surface of the semiconductor layer; and implanting dopant atoms of at least one of a first type and a second type into at least one of a first sidewall and a second sidewall of each of the plurality of trenches of the semiconductor layer.

Abstract: A semiconductor device includes an electrically conductive lead frame which includes a die pad and a plurality of electrically conductive leads, each of the leads in the plurality being spaced apart from the die pad. The semiconductor device further includes first and second integrated switching devices mounted on the die pad, each of the first and second integrated switching devices include electrically conductive gate, source and drain terminals. The source terminal of the first integrated switching device is disposed on a rear surface of the first integrated switching device that faces and electrically connects with the die pad. The drain terminal of the second integrated switching device is disposed on a rear surface of the second integrated switching device that faces and electrically connects with the die pad.