Abstract: A method of forming and structure for through wafer vias and signal transmission lines formed of through wafer vias. The method of forming through wafer vias includes forming an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via through a semiconductor substrate having a top surface and an opposite bottom surface, each through wafer via of the array of through wafer vias extending from the top surface of the substrate to the bottom surface of the substrate.

Abstract: A semiconductor chip integrating a transceiver, an antenna, and a receiver is provided. The transceiver is located on a front side of a semiconductor substrate. A through substrate via provides electrical connection between the transceiver and the receiver located on a backside of the semiconductor substrate. The antenna connected to the transceiver is located in a dielectric layer located on the front side of the substrate. The separation between the reflector plate and the antenna is about the quarter wavelength of millimeter waves, which enhances radiation efficiency of the antenna. An array of through substrate dielectric vias may be employed to reduce the effective dielectric constant of the material between the antenna and the reflector plate, thereby reducing the wavelength of the millimeter wave and enhance the radiation efficiency. A design structure for designing, manufacturing, or testing a design for such a semiconductor chip is also provided.

Abstract: A first field effect transistor includes a gate dielectric and a gate electrode located over a first portion of a top semiconductor layer in a semiconductor-on-insulator (SOI) substrate. A second field effect transistor includes a portion of a buried insulator layer and a source region and a drain region located underneath the buried insulator layer. In one embodiment, the gate electrode of the second field effect transistor is a remaining portion of the top semiconductor layer. In another embodiment, the gate electrode of the second field effect transistor is formed concurrently with the gate electrode of the first field effect transistor by deposition and patterning of a gate electrode layer. The first field effect transistor may be a high performance device and the second field effect transistor may be a high voltage device. A design structure for the semiconductor structure is also provided.

Abstract: A parallel plate capacitor formed in the back end of an integrated circuit employs conductive capacitor plates that are formed simultaneously with the other interconnects on that level of the back end (having the same material, thickness, etc). The capacitor plates are set into the interlevel dielectric using the same process as the other interconnects on that level of the back end (preferably dual damascene). Some versions of the capacitors have perforations in the plates and vertical conductive members connecting all plates of the same polarity, thereby increasing reliability, saving space and increasing the capacitive density compared with solid plates.

Abstract: A design structure for an on-chip high frequency electro-static discharge device is described. In one embodiment, the electro-static discharge structure comprises a first dielectric layer with more than one electrode formed therein. A second dielectric layer with more than one electrode formed therein is located above the first dielectric layer. At least one via connects the more than one electrode in the first dielectric layer with the more than one electrode in the second dielectric layer. A gap is formed through the first dielectric layer and the second dielectric layer, wherein the gap extends between two adjacent electrodes in both the first dielectric layer and the second dielectric layer. A third dielectric layer is disposed over the second dielectric layer, wherein the third dielectric layer hermetically seals the gap to provide electro-static discharge protection on the integrated circuit.

Abstract: A design structure for an on-chip high frequency electro-static discharge device is described. In one embodiment, the electro-static discharge device comprises a substrate and multiple metal level layers disposed on the substrate. Each metal level comprises more than one electrode formed therein and more than one via connecting with some of the electrodes in adjacent metal levels. The device further includes a gap formed about one of the metal level layers, wherein the gap is hermetically sealed to provide electro-static discharge protection for the integrated circuit.

Abstract: A design structure, structure, and method for providing an on-chip variable delay transmission line with a fixed characteristic impedance. A method of manufacturing a transmission line structure includes forming a signal line of the transmission line structure, forming a first ground return structure that causes a first delay and a first characteristic impedance in the transmission line structure, and forming a second ground return structure that causes a second delay and a second characteristic impedance in the transmission line structure. The first delay is different from the second delay, and the first characteristic impedance is substantially the same as the second characteristic impedance.

Abstract: A method for forming an on-chip high frequency electro-static discharge device is described. In one embodiment, a wafer with a multi-metal level wiring is provided and a hermetically sealed gap is formed therein to provide electro-static discharge protection for an integrated circuit.

Abstract: A method for forming an on-chip high frequency electro-static discharge device on an integrated circuit is described. In one embodiment of the method, a capped first dielectric layer with more than one electrode formed therein is provided. A second dielectric layer is deposited over the capped first dielectric layer. A first hard mask dielectric layer is deposited over the second dielectric layer. A cavity trench is formed through the first hard mask dielectric layer and the second dielectric layer to the first dielectric layer, wherein the cavity trench is formed in the first dielectric layer between two adjacent electrodes. At least one via is formed through the second dielectric layer about the cavity trench. A metal trench is formed around each of the at least one via. A release opening is formed over the cavity trench.

Abstract: A design structure, structure, and method for providing an on-chip variable delay transmission line with a fixed characteristic impedance. A method of manufacturing a transmission line structure includes forming a signal line of the transmission line structure, forming a first ground return structure that causes a first delay and a first characteristic impedance in the transmission line structure, and forming a second ground return structure that causes a second delay and a second characteristic impedance in the transmission line structure. The first delay is different from the second delay, and the first characteristic impedance is substantially the same as the second characteristic impedance.

Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a substrate including a silicon layer. Furthermore, the design structure includes a metal layer on a bottom side of the silicon layer and a dielectric layer on a top side of the silicon layer. Additionally, the design structure includes a top-side interconnect of the through-silicon via bandpass filter on a surface of the dielectric layer and a plurality of contacts in the dielectric layer in contact with the top-side interconnect. Further, the design structure includes a plurality of through-silicon vias through the substrate and in contact with the plurality of contacts, respectively, and the metal layer.

Abstract: A method for forming a through-silicon via bandpass filter includes forming a substrate comprising a silicon layer and providing a metal layer on a bottom side of the silicon layer. Additionally, the method includes providing a dielectric layer on a top side of the silicon layer and forming a top-side interconnect of the through-silicon via bandpass filter on a surface of the dielectric layer. Further, the method includes forming a plurality of contacts in the dielectric layer in contact with the top-side interconnect and forming a plurality through-silicon vias through the substrate and in contact with the plurality of contacts, respectively, and the metal layer.

Abstract: Methods for fabricating a coplanar waveguide structure. The method may include forming first and second ground conductors and a signal conductor in a coplanar arrangement between the first and second ground conductors, forming a first coplanar array of substantially parallel shield conductors above the signal conductor and the first and second ground conductors, and forming a second coplanar array of substantially parallel shield conductors below the signal conductor and the first and second ground conductors. The method further includes forming a first plurality of conductive bridges located laterally between the signal conductor and the first ground conductor, and forming a second plurality of conductive bridges located laterally between the signal conductor and the second ground conductor. Each of the first plurality of conductive bridges connects one of the shield conductors in the first array with one of the shield conductors in the second array.

Abstract: Coplanar waveguide structures and design structures for radiofrequency and microwave integrated circuits. The coplanar waveguide structure includes a signal conductor and ground conductors generally coplanar with the signal conductor. The signal conductor is disposed between upper and lower arrays of substantially parallel shield conductors. Conductive bridges, which are electrically isolated from the signal conductor, are located laterally between the signal conductor and each of the ground conductors. Pairs of the conductive bridges connect one of the shield conductors in the first array with one of the shield conductors in the second array to define closed loops encircling the signal line.

Abstract: On-chip integrated variable inductors, methods of making and tuning an on-chip integrated variable inductor, and design structures embodying a circuit containing the on-chip integrated variable inductor. The inductor generally includes a signal line configured to carry an electrical signal, a ground line positioned in proximity to the signal line, and at least one control unit electrically coupled with the ground line. The at least one control unit is configured to open and close switch a current path connecting the ground line with a ground potential so as to change an inductance of the signal line.

Abstract: An LC tack structure. The structure, including a set of wiring levels on top of a semiconductor substrate, the wiring levels stacked on top of each other from a lowest wiring level nearest the substrate to a highest wiring level furthest from the substrate; an inductor in the highest wiring level, the inductor confined within a perimeter of a region of the highest wiring level; and a varactor formed in the substrate, the varactor aligned completely under the perimeter of the region of the highest wiring level. The structure may additionally include an electric shield in a wiring level of the set of wiring levels between the lowest wiring level and the highest wiring level. Alternatively, the inductor includes a magnetic core and alternating electrically non-magnetic conductive metal coils and magnetic coils around the core.

Abstract: A structure includes a substrate comprising a region having a circuit or device which is sensitive to electrical noise. Additionally, the structure includes a first isolation structure extending through an entire thickness of the substrate and surrounding the region and a second isolation structure extending through the entire thickness of the substrate and surrounding the region.

Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. The design structure comprises: a conductive structure surrounding and accommodating a circuit or a circuit device arranged on a substrate and at least one feed through capacitor and one transmission line associated with the conductive structure and providing the power supply and signals to the circuit or circuit device respectively. The design structure also comprises a shielding structure surrounding a circuit or a circuit device arranged on a substrate and at least one feed through capacitor or a transmission line arranged on a side of the shielding structure.

Abstract: An electromagnetic shielding structure that includes a conductive structure surrounding and accommodating a circuit or a circuit device arranged on a substrate. At least one feed through device is associated with the conductive structure and provides signals to the circuit or circuit device. The method includes forming a shielding structure so that the shielding structure at least one of is at least partially arranged within the substrate and surrounds the circuit or circuit device and associating at least one feed through device with the shielding structure.

Abstract: A microelectronic device and method of making the microelectronic device is provided. A dielectric substrate having first and second surfaces is provided. A first component, located in the dielectric substrate between the first and second surfaces of the dielectric substrate is formed. The first component includes a first interface and a second interface. A second component located in the dielectric substrate and spaced relative to the first component is formed, and a first low permittivity material is formed having a predetermined thickness and a first and second surface, the first surface of the low permittivity material is adjacent to or in contact with a first portion of the first interface of the first component. The first low permittivity material substantially reduces capacitive parasitics of the first component, resulting in a substantially higher characteristic impedance of the first component during operation of the microelectronic device.