Patents by Inventor Hanyi Ding
Hanyi Ding has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8399927Abstract: A first field effect transistor includes a gate dielectric and a gate electrode located over a first portion of a top semiconductor layer in a semiconductor-on-insulator (SOI) substrate. A second field effect transistor includes a portion of a buried insulator layer and a source region and a drain region located underneath the buried insulator layer. In one embodiment, the gate electrode of the second field effect transistor is a remaining portion of the top semiconductor layer. In another embodiment, the gate electrode of the second field effect transistor is formed concurrently with the gate electrode of the first field effect transistor by deposition and patterning of a gate electrode layer. The first field effect transistor may be a high performance device and the second field effect transistor may be a high voltage device. A design structure for the semiconductor structure is also provided.Type: GrantFiled: February 7, 2012Date of Patent: March 19, 2013Assignee: International Business Machines CorporationInventors: Hanyi Ding, Kai D. Feng, Zhong-Xiang He, Zhenrong Jin, Xuefeng Liu, Yun Shi
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Patent number: 8384224Abstract: A method of forming and structure for through wafer vias and signal transmission lines formed of through wafer vias. The structure includes, a semiconductor substrate having a top surface and an opposite bottom surface; and an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via, each through wafer via of the array of through wafer vias extending from the top surface of to the bottom surface of the substrate, the at least one electrically conductive via electrically isolated from the substrate.Type: GrantFiled: August 8, 2008Date of Patent: February 26, 2013Assignee: International Business Machines CorporationInventors: Hanyi Ding, Alvin Jose Joseph, Anthony Kendall Stamper
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Publication number: 20130044838Abstract: A voltage controlled oscillator (VCO), IC and CMOS IC including the VCO. The VCO includes an LC tank circuit, a pair of cross-coupled devices connected to the tank circuit and driving a pair of buffers. Each of the pair of cross-coupled devices includes a field effect transistor (FET) with an independently controllable body, e.g., the surface layer of a Silicon on Insulator (SOI) chip or the surface well of a multi-well chip. Diodes in the multi-well structure are biased off in each device.Type: ApplicationFiled: August 17, 2011Publication date: February 21, 2013Applicant: International Business Machines CorporationInventors: Hanyi Ding, Pinping Sun, Hailing Wang
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Patent number: 8378448Abstract: A set of metal line structures including a signal transmission metal line and a capacitively-grounded inductively-signal-coupled metal line is embedded in a dielectric material layer. A capacitor is serially connected between the capacitively-grounded inductively-signal-coupled metal line and a local electrical ground, which may be on the input side or on the output side. The set of metal line structures and the capacitor collective provide a frequency dependent inductor. The Q factor of the frequency dependent inductor has multiple peaks that enable the operation of the frequency dependent inductor at multiple frequencies. Multiple capacitively-grounded inductively-signal-coupled metal lines may be provided in the frequency-dependent inductor, each of which is connected to the local electrical ground through a capacitor. By selecting different capacitance values for the capacitors, multiple values of the Q-factor may be obtained in the frequency dependent inductor at different signal frequencies.Type: GrantFiled: December 7, 2009Date of Patent: February 19, 2013Assignee: International Business Machines CorporationInventors: Hanyi Ding, Wayne H. Woods, Jr.
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Publication number: 20120326798Abstract: A transmission wiring structure, associated design structure and associated method for forming the same. A structure is disclosed having: a plurality of wiring levels formed on a semiconductor substrate; a pair of adjacent first and second signal lines located in the wiring levels, wherein the first signal line comprises a first portion formed on a first wiring level and a second portion formed on a second wiring level; a primary dielectric structure having a first dielectric constant located between the first portion and a ground shield; and a secondary dielectric structure having a second dielectric constant different than the first dielectric constant, the secondary dielectric structure located between the second portion and the ground shield, and the second dielectric layer extending co-planar with the second portion and having a length that is substantially the same as the second portion.Type: ApplicationFiled: June 24, 2011Publication date: December 27, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Hanyi Ding, Kai D. Feng, Zhong-Xiang He, Xuefeng Liu
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Publication number: 20120329219Abstract: A method of forming and structure for through wafer vias and signal transmission lines formed of through wafer vias. The method of forming through wafer vias includes forming an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via through a semiconductor substrate having a top surface and an opposite bottom surface, each through wafer via of the array of through wafer vias extending from the top surface of the substrate to the bottom surface of the substrate.Type: ApplicationFiled: September 6, 2012Publication date: December 27, 2012Applicant: International Business Machines CorporationInventors: Hanyi Ding, Alvin Jose Joseph, Anthony Kendall Stamper
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Patent number: 8338920Abstract: An integrated circuit package includes an integrated circuit with one or more on-chip inductors. A package cover covers the integrated circuit. A magnetic material is provided between the integrated circuit and the package cover. The magnetic material may be a soft magnetic thin film. The magnetic material may be affixed to the package cover by an adhesive. The magnetic material may be formed directly on the package cover by one of deposition, sputtering or spraying. The magnetic material may be affixed to the integrated circuit.Type: GrantFiled: May 8, 2007Date of Patent: December 25, 2012Assignee: International Business Machines CorporationInventors: John Michael Cotte, Hanyi Ding, Kai Di Feng, Zhong-Xiang He, Nils D. Hoivik, Xuefeng Liu
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Publication number: 20120273966Abstract: An integrated circuit (IC) interconnect structure that includes a first via positioned in a dielectric and coupled to a high current device at one end, and a buffer metal segment positioned in a dielectric and coupled to the first via at an opposite end thereof. The buffer metal segment includes a plurality of electrically insulating inter-dielectric (ILD) pads forming an ILD cheesing pattern thereon, to direct current. The IC interconnect structure further includes a second via positioned in a dielectric formed over the buffer metal segment and coupled to the buffer metal segment at one end and a metal power line formed in a dielectric and coupled to the second via at an opposite end thereof. The use of the ILD pads on the buffer metal segment enables a more even distribution of current along the metal power line.Type: ApplicationFiled: June 22, 2012Publication date: November 1, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Hanyi Ding, Ronald G. Filippi, Jong-Ru Guo, Ping-Chuan Wang
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Patent number: 8299566Abstract: A method of forming and structure for through wafer vias and signal transmission lines formed of through wafer vias. The method of forming through wafer vias includes forming an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via through a semiconductor substrate having a top surface and an opposite bottom surface, each through wafer via of the array of through wafer vias extending from the top surface of the substrate to the bottom surface of the substrate.Type: GrantFiled: August 8, 2008Date of Patent: October 30, 2012Assignee: International Business Machines CorporationInventors: Hanyi Ding, Alvin Jose Joseph, Anthony Kendall Stamper
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Publication number: 20120267794Abstract: Structures with high-Q value inductors, design structure for high-Q value inductors and methods of fabricating such structures is disclosed herein. A method in a computer-aided design system for generating a functional design model of an inductor is also provided. The method includes: generating a functional representation of a plurality of vertical openings simultaneously formed in a substrate, wherein a first of the plurality of vertical openings is used as through silicon vias and is etched deeper than a second of the plurality of vertical openings used for high-Q inductors; generating a functional representation of a dielectric layer formed in the plurality of vertical openings; and generating a functional representation of a metal layer deposited on the dielectric layer in the plurality of vertical.Type: ApplicationFiled: June 28, 2012Publication date: October 25, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Hanyi DING, Mete ERTURK, Robert A. GROVES, Zhong-Xiang HE, Peter J. LINDGREN, Anthony K. STAMPER
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Publication number: 20120264289Abstract: An integrated circuit (IC) interconnect structure that includes a first via positioned in a dielectric and coupled to a high current device at one end, and a buffer metal segment positioned in a dielectric and coupled to the first via at an opposite end thereof. The buffer metal segment includes a plurality of electrically insulating inter-dielectric (ILD) pads forming an ILD cheesing pattern thereon, to direct current. The IC interconnect structure further includes a second via positioned in a dielectric formed over the buffer metal segment and coupled to the buffer metal segment at one end and a metal power line formed in a dielectric and coupled to the second via at an opposite end thereof. The use of the ILD pads on the buffer metal segment enables a more even distribution of current along the metal power line.Type: ApplicationFiled: June 22, 2012Publication date: October 18, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Hanyi Ding, Ronald G. Filippi, Jong-Ru Guo, Ping-Chuan Wang
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Publication number: 20120266116Abstract: A semiconductor chip integrating a transceiver, an antenna, and a receiver is provided. The transceiver is located on a front side of a semiconductor substrate. A through substrate via provides electrical connection between the transceiver and the receiver located on a backside of the semiconductor substrate. The antenna connected to the transceiver is located in a dielectric layer located on the front side of the substrate. The separation between the reflector plate and the antenna is about the quarter wavelength of millimeter waves, which enhances radiation efficiency of the antenna. An array of through substrate dielectric vias may be employed to reduce the effective dielectric constant of the material between the antenna and the reflector plate, thereby reducing the wavelength of the millimeter wave and enhance the radiation efficiency. A design structure for designing, manufacturing, or testing a design for such a semiconductor chip is also provided.Type: ApplicationFiled: June 27, 2012Publication date: October 18, 2012Applicant: International Business Machines CorporationInventors: Hanyi Ding, Kai D. Feng, Zhong-Xiang He, Zhenrong Jin, Xuefeng Liu
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Patent number: 8279572Abstract: A design structure for an on-chip high frequency electro-static discharge device is described. In one embodiment, the electro-static discharge structure comprises a first dielectric layer with more than one electrode formed therein. A second dielectric layer with more than one electrode formed therein is located above the first dielectric layer. At least one via connects the more than one electrode in the first dielectric layer with the more than one electrode in the second dielectric layer. A gap is formed through the first dielectric layer and the second dielectric layer, wherein the gap extends between two adjacent electrodes in both the first dielectric layer and the second dielectric layer. A third dielectric layer is disposed over the second dielectric layer, wherein the third dielectric layer hermetically seals the gap to provide electro-static discharge protection on the integrated circuit.Type: GrantFiled: June 23, 2008Date of Patent: October 2, 2012Assignee: International Business Machines CorporationInventors: Hanyi Ding, Kai D. Feng, Zhong-Xiang He, Xuefeng Liu, Anthony K. Stamper
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Publication number: 20120212303Abstract: A method, structure, and design structure for a through-silicon-via Wilkinson power divider. A method includes: forming an input on a first side of a substrate; forming a first leg comprising a first through-silicon-via formed in the substrate, wherein the first leg electrically connects the input and a first output; forming a second leg comprising a second through-silicon-via formed in the substrate, wherein the second leg electrically connects the input and a second output, and forming a resistor electrically connected between the first output and the second output.Type: ApplicationFiled: April 25, 2012Publication date: August 23, 2012Applicant: International Business Machines CorporationInventors: Hanyi DING, Alvin J. JOSEPH, Wayne H. WOODS, JR.
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Patent number: 8237286Abstract: An integrated circuit (IC) interconnect structure that includes a first via positioned in a dielectric and coupled to a high current device at one end, and a buffer metal segment positioned in a dielectric and coupled to the first via at an opposite end thereof. The buffer metal segment includes a plurality of electrically insulating inter-dielectric (ILD) pads forming an ILD cheesing pattern thereon, to direct current. The IC interconnect structure further includes a second via positioned in a dielectric formed over the buffer metal segment and coupled to the buffer metal segment at one end and a metal power line formed in a dielectric and coupled to the second via at an opposite end thereof. The use of the ILD pads on the buffer metal segment enables a more even distribution of current along the metal power line.Type: GrantFiled: April 15, 2010Date of Patent: August 7, 2012Assignee: International Business Machines CorporationInventors: Hanyi Ding, Ronald G. Filippi, Jong-Ru Guo, Ping-Chuan Wang
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Publication number: 20120194302Abstract: A design structure, structure, and method for providing an on-chip variable delay transmission line with a fixed characteristic impedance. A method of manufacturing a transmission line structure includes forming a signal line of the transmission line structure, forming a first ground return structure that causes a first delay and a first characteristic impedance in the transmission line structure, and forming a second ground return structure that causes a second delay and a second characteristic impedance in the transmission line structure. The first delay is different from the second delay, and the first characteristic impedance is substantially the same as the second characteristic impedance.Type: ApplicationFiled: April 6, 2012Publication date: August 2, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Hanyi DING, Wayne H. WOODS, JR.
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Patent number: 8232115Abstract: A test structure for a through-silicon-via (TSV) in a semiconductor chip includes a first contact, the first contact being electrically connected to a first TSV; and a second contact, wherein the first contact, second contact, and the first TSV form a first channel, and a depth of the first TSV is determined based on a resistance of the first channel. A method of determining a depth of a through-silicon-via (TSV) in a semiconductor chip includes etching a first TSV into the semiconductor chip; forming a first channel, the first channel comprising the first TSV, a first contact electrically connected to the first TSV, and a second contact; connecting a current source to the second contact; determining a resistance across the first channel; and determining a depth of the first TSV based on the resistance of the first channel.Type: GrantFiled: September 25, 2009Date of Patent: July 31, 2012Assignee: International Business Machines CorporationInventors: Hanyi Ding, Kai D. Feng, Ping-Chuan Wang, Zhijian Yang
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Patent number: 8232851Abstract: A Lange coupler having a first plurality of lines on a first level and a second plurality of lines on a second level. At least one line on the first level is cross-coupled to a respective line on the second level via electromagnetic waves traveling through the first and second plurality of lines. The first and second plurality of lines may be made of metal, and the first level may be higher than the second level. A substrate may be provided into which the first and second plurality of lines are etched so as to define an on-chip Lange coupler.Type: GrantFiled: March 16, 2009Date of Patent: July 31, 2012Assignee: International Business Machines CorporationInventors: Hanyi Ding, Kwan Him Lam
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Patent number: 8232173Abstract: Structures with high-Q value inductors, design structure for high-Q value inductors and methods of fabricating such structures is disclosed herein. A method in a computer-aided design system for generating a functional design model of an inductor is also provided. The method includes: generating a functional representation of a plurality of vertical openings simultaneously formed in a substrate, wherein a first of the plurality of vertical openings is used as through silicon vias and is etched deeper than a second of the plurality of vertical openings used for high-Q inductors; generating a functional representation of a dielectric layer formed in the plurality of vertical openings; and generating a functional representation of a metal layer deposited on the dielectric layer in the plurality of vertical.Type: GrantFiled: November 1, 2010Date of Patent: July 31, 2012Assignee: International Business Machines CorporationInventors: Hanyi Ding, Mete Erturk, Robert A. Groves, Zhong-Xiang He, Peter J. Lindgren, Anthony K. Stamper
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Patent number: 8232920Abstract: A semiconductor chip integrating a transceiver, an antenna, and a receiver is provided. The transceiver is located on a front side of a semiconductor substrate. A through substrate via provides electrical connection between the transceiver and the receiver located on a backside of the semiconductor substrate. The antenna connected to the transceiver is located in a dielectric layer located on the front side of the substrate. The separation between the reflector plate and the antenna is about the quarter wavelength of millimeter waves, which enhances radiation efficiency of the antenna. An array of through substrate dielectric vias may be employed to reduce the effective dielectric constant of the material between the antenna and the reflector plate, thereby reducing the wavelength of the millimeter wave and enhance the radiation efficiency. A design structure for designing, manufacturing, or testing a design for such a semiconductor chip is also provided.Type: GrantFiled: August 7, 2008Date of Patent: July 31, 2012Assignee: International Business Machines CorporationInventors: Hanyi Ding, Kai D. Feng, Zhong-Xiang He, Zhenrong Jin, Xuefeng Liu