Patents by Inventor Hao A. Chen

Hao A. Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11991581
    Abstract: A system and method of a base station are configured to enable a multi-shot network parameter optimization. The method includes generating one or more specified Key Performance Indicators (KPI) constraints based on a selected set of KPIs. The method also includes adjusting common beam parameters to tune a common beam based on the selected set of KPIs. The common beam is tuned to satisfy the one or more specified KPI constraints. The method also includes adjusting handover A2 and A5 parameters based on searching within a three-dimensional space defined by specified A2 and A5 thresholds. The method further includes transmitting one or more signals based on the adjusted the common beam parameters and the adjusted handover A2 and A5 parameters.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: May 21, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hao Chen, Lianjun Li, Zhou Zhou, Yan Xin, Jianzhong Zhang
  • Patent number: 11991860
    Abstract: A fluid cooling device includes a bottom plate, an adhesive layer and a spray cooling cover. The bottom plate includes a substrate and a chip, and the spray cooling cover is fixed on the bottom plate by an adhesive layer. In addition, the spray cooling cover includes a fluid inlet and a plurality of fluid outlets to utilize a working fluid to cool the chip directly.
    Type: Grant
    Filed: October 28, 2021
    Date of Patent: May 21, 2024
    Assignee: AURAS TECHNOLOGY CO., LTD.
    Inventors: Chien-Yu Chen, Wei-Hao Chen
  • Patent number: 11990471
    Abstract: Gate cutting techniques disclosed herein form gate isolation fins to isolate metal gates of multigate devices from one another before forming the multigate devices, and in particular, before forming the metal gates of the multigate devices. An exemplary device includes a first multigate device having first source/drain features and a first metal gate that surrounds a first channel layer and a second multigate device having second source/drain features and a second metal gate that surrounds a second channel layer. A gate isolation fin, which separates the first metal gate and the second metal gate, includes a first dielectric layer having a first dielectric constant and a second dielectric layer having a second dielectric constant disposed over the first dielectric layer. The second dielectric constant is less than the first dielectric constant. A gate isolation end cap may be disposed on the gate isolation fin to provide additional isolation.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Chiang, Shi Ning Ju, Guan-Lin Chen, Kuan-Ting Pan, Chih-Hao Wang
  • Patent number: 11991854
    Abstract: A wireless charging base is provided, and is mainly applied to electronic devices such as a mobile phone and a tablet computer. The wireless charging base includes a charging panel, configured to charge the electronic device. The charging panel includes a first air vent and a second air vent. A first base plate is disposed on an upper surface of the charging panel, is located at an end of the charging panel, and is configured to support the electronic device when the electronic device is being charged. The first base plate includes a third air vent. A second base plate is disposed on the lower surface of the charging panel, is located at the same end as the first base plate, and is configured to support the charging panel. The second base plate includes a fourth air vent.
    Type: Grant
    Filed: March 25, 2022
    Date of Patent: May 21, 2024
    Assignee: Huawei Digital Power Technologies Co., Ltd.
    Inventors: Hao Wu, Jun Chen, Yongwang Xiao, Jun Li
  • Patent number: 11991500
    Abstract: A speaker comprises a housing, a transducer residing inside the housing, and at least one sound guiding hole located on the housing. The transducer generates vibrations. The vibrations produce a sound wave inside the housing and cause a leaked sound wave spreading outside the housing from a portion of the housing. The at least one sound guiding hole guides the sound wave inside the housing through the at least one sound guiding hole to an outside of the housing. The guided sound wave interferes with the leaked sound wave in a target region. The interference at a specific frequency relates to a distance between the at least one sound guiding hole and the portion of the housing.
    Type: Grant
    Filed: April 23, 2023
    Date of Patent: May 21, 2024
    Assignee: SHENZHEN SHOKZ CO., LTD.
    Inventors: Xin Qi, Fengyun Liao, Jinbo Zheng, Qian Chen, Hao Chen
  • Patent number: 11990575
    Abstract: A light-emitting device comprises a substrate comprising a sidewall, a first top surface, and a second top surface, wherein the second top surface is closer to the sidewall of the substrate than the first top surface to the sidewall of the substrate; a semiconductor stack formed on the substrate comprising a first semiconductor layer, an active layer, and a second semiconductor layer; a dicing street surrounding the semiconductor stack, and exposing the first top surface and the second top surface of the substrate; a protective layer covering the semiconductor stack; a reflective layer comprising a Distributed Bragg Reflector structure covering the protective layer; and a cap layer covering the reflective layer, wherein the second top surface of the substrate is not covered by the protective layer, the reflective layer, and the cap layer.
    Type: Grant
    Filed: June 5, 2023
    Date of Patent: May 21, 2024
    Assignee: EPISTAR CORPORATION
    Inventors: Hsin-Ying Wang, Chih-Hao Chen, Chien-Chih Liao, Chao-Hsing Chen, Wu-Tsung Lo, Tsun-Kai Ko, Chen Ou
  • Publication number: 20240159808
    Abstract: An anechoic chamber and a construction method thereof are provided, the anechoic chamber includes a top surface, being a polygon; trapezoid surfaces, corresponding to edges of top surface, upper edge lengths of trapezoid surface being equal to edge lengths of top surface, trapezoid surfaces being connected to edges of top surface through the upper edges, the trapezoid surfaces being sequentially connected along a circumferential direction of top surface, and being at angle to the top surface; rectangular surfaces, corresponding to the trapezoid surfaces, upper edge lengths of rectangular surface being equal to lower edge lengths of trapezoid surface, rectangular surfaces being connected to the trapezoid surfaces through the upper edges, the rectangular surfaces being sequentially connected along a circumferential direction of the lower edges of trapezoid surfaces, and being perpendicular to the top surface; and an absorbing material, disposed on the top surface, the trapezoid surfaces and the rectangular surf
    Type: Application
    Filed: November 7, 2023
    Publication date: May 16, 2024
    Inventors: Zibin He, Deqiang Song, Hao Xing, Huiru Zhang, Shujuan Song, Hao Chai, Zheng Li, Quan Chen, Yizhou Wang, Wenyu Cheng
  • Publication number: 20240162094
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate, a conductive feature on the substrate, and an electrical connection structure on the conductive feature. The electrical connection includes a first grain made of a first metal material, and a first inhibition layer made of a second metal layer that is different than the first metal material. The first inhibition layer extends vertically along a first side of a grain boundary of the first grain and laterally along a bottom of the grain boundary of the first grain.
    Type: Application
    Filed: January 5, 2024
    Publication date: May 16, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Chuan CHIU, Jia-Chuan YOU, Chia-Hao CHANG, Chun-Yuan CHEN, Tien-Lu LIN, Yu-Ming LIN, Chih-Hao WANG
  • Publication number: 20240162308
    Abstract: The present disclosure provides a semiconductor structure with having a source/drain feature with a central cavity, and a source/drain contact feature formed in central cavity of the source/drain region, wherein the source/drain contact feature is nearly wrapped around by the source/drain region. The source/drain contact feature may extend to a lower most of a plurality semiconductor layers.
    Type: Application
    Filed: February 9, 2023
    Publication date: May 16, 2024
    Inventors: Pin Chun SHEN, Che Chia CHANG, Li-Ying WU, Jen-Hsiang LU, Wen-Chiang HONG, Chun-Wing YEUNG, Ta-Chun LIN, Chun-Sheng LIANG, Shih-Hsun CHANG, Chih-Hao CHANG, Yi-Hsien CHEN
  • Publication number: 20240162220
    Abstract: A capacitor on a fin structure includes a fin structure. A dielectric layer covers the fin structure. A first electrode extension is embedded within the fin structure. A first electrode penetrates the dielectric layer and contacts the first electrode extension. A second electrode and a capacitor dielectric layer are disposed within the dielectric layer. The capacitor dielectric layer surrounds the second electrode, and the capacitor dielectric layer is between the second electrode and the first electrode extension.
    Type: Application
    Filed: December 8, 2022
    Publication date: May 16, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hsin-Yu Chen, Chun-Hao Lin, Yuan-Ting Chuang, Shou-Wei Hsieh
  • Publication number: 20240158734
    Abstract: The present application belongs to the technical field of biopharmaceutical production devices, and discloses a culture vessel carrier automatic slide mechanism and a shaker incubator, by means of which a shake flask/shake tube/well plate carrier assembly can automatically slide in and out relative to an incubator main body. The culture vessel carrier automatic slide mechanism comprises a slide protective housing and is provided with a culture vessel carrier bearing member. A first slide rail and a second slide rail are arranged below the culture vessel carrier bearing member. The second slide rail is arranged below the culture vessel carrier bearing member and located above the first slide rail, and the first slide rail is arranged inside the incubator main body on a fixed base that does not slide.
    Type: Application
    Filed: December 7, 2021
    Publication date: May 16, 2024
    Inventors: Hao Chen, Kee Wee Tan, Jie Ding
  • Publication number: 20240160928
    Abstract: A method for enhancing kernel reparameterization of a non-linear machine learning model includes providing a predefined machine learning model, expanding a kernel of the predefined machine learning model with a non-linear network for convolution operation of the predefined machine learning model to generate the non-linear machine learning model, training the non-linear machine learning model, reparameterizing the non-linear network back to a kernel for convolution operation of the non-linear machine learning model to generate a reparameterized machine learning model, and deploying the reparameterized machine learning model to an edge device.
    Type: Application
    Filed: November 10, 2023
    Publication date: May 16, 2024
    Applicant: MEDIATEK INC.
    Inventors: Po-Hsiang Yu, Hao Chen, Cheng-Yu Yang, Peng-Wen Chen
  • Publication number: 20240161013
    Abstract: A reparameterization method for initializing a machine learning model includes initializing a prefix layer of a first low dimensional layer in the machine learning model and a postfix layer of the first low dimensional layer, inverting the prefix layer to generate an inverse prefix layer of the first low dimensional layer, inverting the postfix layer to generate an inverse postfix layer of the first low dimensional layer, combining the inverse prefix layer, the first low dimensional layer and the inverse postfix layer to form a high dimensional layer, generating parallel operation layers from the high dimensional layer, and assigning initial weights to the parallel operation layers.
    Type: Application
    Filed: November 3, 2023
    Publication date: May 16, 2024
    Applicant: MEDIATEK INC.
    Inventors: Cheng-Yu Yang, Hao Chen, Po-Hsiang Yu, Peng-Wen Chen
  • Publication number: 20240163075
    Abstract: The present disclosure provides a privacy computing method based on homomorphic encryption, which includes steps as follows. The ciphertext data is received, where the ciphertext data has a floating-point homomorphic encryption data structure, and the floating-point homomorphic encryption data structure of the ciphertext data includes the ciphertext mantissa, exponent parameter and gain parameter. The gain parameter sets the precision of the floating point corresponding to the ciphertext mantissa. The exponent parameter is adapted to multiplication or division. The artificial intelligence model performs operations on the ciphertext data to return the ciphertext result.
    Type: Application
    Filed: February 17, 2023
    Publication date: May 16, 2024
    Inventors: Yu Te KU, Chih-Fan HSU, Wei-Chao CHEN, Feng-Hao LIU, Ming-Ching CHANG
  • Publication number: 20240158225
    Abstract: A micro electro mechanical system (MEMS) device and a method for manufacturing the same are provided. The MEMS device includes a substrate, a polymer film on the substrate and having a lower surface facing toward the substrate, a cavity passing through the substrate, and coil structures on the substrate and in the polymer film. The polymer film includes a corrugation pattern on the lower surface of the polymer film. A portion of the polymer film is exposed in the cavity.
    Type: Application
    Filed: December 6, 2022
    Publication date: May 16, 2024
    Inventors: Jung-Hao CHANG, Weng-Yi CHEN
  • Publication number: 20240160919
    Abstract: In aspects of the disclosure, a method, a system, and a computer-readable medium are provided. The method of building a kernel reparameterization for replacing a convolution-wise operation kernel in training of a neural network comprises selecting one or more blocks from tensor blocks and operations; and connecting the selected one or more blocks with the selected operations to build the kernel reparameterization. The kernel reparameterization has a dimension same as that of the convolution-wise operation kernel.
    Type: Application
    Filed: October 17, 2023
    Publication date: May 16, 2024
    Inventors: Po-Hsiang Yu, Hao Chen, Peng-Wen Chen, Cheng-Yu Yang
  • Publication number: 20240162349
    Abstract: A device includes a semiconductor fin, and a gate stack on sidewalls and a top surface of the semiconductor fin. The gate stack includes a high-k dielectric layer, a work-function layer overlapping a bottom portion of the high-k dielectric layer, and a blocking layer overlapping a second bottom portion of the work-function layer. A low-resistance metal layer overlaps and contacts the work-function layer and the blocking layer. The low-resistance metal layer has a resistivity value lower than second resistivity values of both of the work-function layer and the blocking layer. A gate spacer contacts a sidewall of the gate stack.
    Type: Application
    Filed: January 24, 2024
    Publication date: May 16, 2024
    Inventors: Chung-Chiang Wu, Po-Cheng Chen, Kuo-Chan Huang, Hung-Chin Chung, Hsien-Ming Lee, Chien-Hao Chen
  • Publication number: 20240160934
    Abstract: A method for removing branches from trained deep learning models is provided. The method includes steps (i)-(v). In step (i), a trained model is obtained. The trained model has a branch structure involving one or more original convolutional layers and a shortcut connection. In step (ii), the shortcut connection is removed from the branch structure. In step (iii), a reparameterization model is built by linearly expanding each of the original convolutional layers into a reparameterization block in the reparameterization model. In step (iv), parameters of the reparameterization blocks are optimized by training the reparameterization model. In step (v), each of the optimized reparameterization blocks is transformed into a reparameterized convolutional layer to form a branchless structure that replaces the branch structure in the trained model.
    Type: Application
    Filed: August 16, 2023
    Publication date: May 16, 2024
    Inventors: Hao CHEN, Po-Hsiang YU, Yu-Cheng LO, Cheng-Yu YANG, Peng-Wen CHEN
  • Publication number: 20240162382
    Abstract: The present disclosure provides a light-emitting package. The light-emitting package includes a main body, a cavity disposed in the cavity, a base plane in the cavity and a light-emitting element. The light-emitting element is disposed in the cavity and connected to the base plane. The light-emitting element includes a substrate and a semiconductor stack on the substrate. The substrate includes a side wall, and the side wall incudes a first cutting trace. The main body includes a step portion disposed in the cavity and it surrounds the light-emitting element. The step portion comprises a first height relative to base plane, and the first cutting trace comprises a second height relative to the base plane. The second height is greater than the first height.
    Type: Application
    Filed: November 10, 2023
    Publication date: May 16, 2024
    Inventors: Wu-Tsung LO, Chih-Hao CHEN, Wei-Che WU, Heng-Ying CHO, Tsun-Kai KO
  • Publication number: 20240162227
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The method includes forming a first dielectric feature between first and the second fin structures, wherein each first and second fin structure includes first semiconductor layers and second semiconductor layers alternatingly stacked and in contact with the first dielectric layer. The method also includes removing the second semiconductor layers so that the first semiconductor layers of the first and second fin structures extend laterally from a first side and a second side of the first dielectric feature, respectively, trimming the first dielectric feature so that the first dielectric feature has a reduced thickness on both first and the second sides, and forming a gate electrode layer to surround each of the first semiconductor layers of the first and second fin structures.
    Type: Application
    Filed: November 19, 2023
    Publication date: May 16, 2024
    Inventors: Guan-Lin CHEN, Kuo-Cheng CHIANG, Shi Ning JU, Jung-Chien CHENG, Chih-Hao WANG, Kuan-Lun CHENG