Abstract: A semiconductor device includes channel members vertically stacked, a gate structure wrapping around the channel members, a gate spacer disposed on sidewalls of the gate structure, an epitaxial feature abutting the channel members, and an inner spacer layer interposing the gate structure and the epitaxial feature. In a top view of the semiconductor device, the inner spacer layer has side portions in physical contact with the gate spacer and a middle portion stacked between the side portions. In a lengthwise direction of the channel members, the middle portion of the inner spacer layer is thicker than the side portions of the inner spacer layer.

Abstract: A channel hiatus correction method for an HDMI device is provided. A recovery code from scrambled data of the stream is obtained. A liner feedback shift register (LFSR) value of channels of the HDMI port is obtained based on the recovery code and the scrambled data of the stream. The stream is de-scrambled according to the LFSR value of the channels of the HDMI port. Video data is displayed according to the de-scrambled stream.

Abstract: Provided is a light-emitting panel comprising a substrate, a plurality of light-emitting device, and a reflection sheet, wherein the plurality of light-emitting devices and the reflection sheet are disposed on the same side of the substrate, the reflection sheet comprises a plurality of first through-holes, which are in one-to-one correspondence with the plurality of light-emitting devices, and the reflection sheet at an edge of the plurality of first through-holes is configured to wrap around an edge of the plurality of light-emitting device, and a gap between an edge of the plurality of first through-holes and an edge adjacent to the plurality of light-emitting devices is less than 0.1 mm, so that a distance between the edge of the plurality of first through holes and the edge of the plurality of light-emitting devices is reduced, and the size and width of the windowed area are reduced.

Abstract: A charging circuitry includes a power electronic converter, a current sensor, a voltage boost/buck controller and a charging mode controller. The power electronic converter is configured to charge or discharge a supercapacitor according to a control command. The current sensor is coupled to the supercapacitor for detecting a first sensed voltage and a second sensed voltage. The voltage boost/buck controller is configured to generate the control command and a current command according to the first and second sensed voltages and an overall feedback. The charging mode controller is configured to generate a current feedback and a voltage feedback to the voltage boost/buck controller according to a driving voltage, the current command and a third sensed voltage of the supercapacitor. The third sensed voltage, the current feedback and the voltage feedback are superposed as the overall feedback and then inputted to the same input terminal of the voltage boost/buck converter.

Abstract: Disclosed is a method and system for grid connection management of renewable energy generation, the method comprises: obtaining operating condition data of a first power supply, a second power supply, a power grid, and a load in a preset period; establishing a first optimal control model according to the first condition data, and establishing a second optimal control model; monitoring grid connection management status of the first optimal control model and the second optimal control model; analyzing stability when the first optimal control model is switched to the second optimal control model. The beneficial effects of this disclosure are: completing the switch from the first optimal control model to the second optimal control model in the renewable energy generation grid connection management, which improves the smoothness of control model switching under different load conditions in the renewable energy generation process.

Abstract: A pixel detection device includes a data line, a pixel circuit, and a detection circuit. Pixel circuit is coupled to a system high voltage source, a system low voltage source, and a first reference voltage source. Detection circuit is coupled to data line and pixel circuit, and is configured to receive a driving signal and a detection control signal. Detection circuit forms a first detection loop with the system low voltage source and the data line so as to detect whether the pixel circuit is abnormal according to the driving signal and the detection control signal in a first stage. Detection circuit forms a second detection loop with the first reference voltage source, the system low voltage source, the pixel circuit, and the data line so as to detect whether the pixel circuit is abnormal according to the driving signal and the detection control signal in a second stage.

Abstract: An implantable micro-biosensor a substrate, a first electrode, a second electrode, a third electrode, and a chemical reagent layer. The first electrode is disposed on the substrate and used as a counter electrode. The second electrode is disposed on the substrate and spaced apart from the first electrode. The third electrode is disposed on the substrate and used as a working electrode. The chemical reagent layer at least covers a sensing section of the third electrode so as to permit the third electrode to selectively cooperate with the first electrode or the first and second electrodes to measure a physiological signal in response to the physiological parameter of the analyte.

Abstract: A route recommendation method, an electronic device, and a storage medium are provided, which relate to the field of data processing and especially relate to the field of intelligent recommendation. The method includes: receiving a route recommendation request, wherein the route recommendation request comprises N-dimension itinerary label information; selecting M theme routes from a theme route library according to the N-dimension itinerary label information; determining a recommended route from the M theme routes, wherein the selecting the M theme routes from the theme route library according to the N-dimension itinerary label information, comprises: selecting at least one theme route from the theme route library according to i-th-dimension itinerary label information in the N-dimension itinerary label information and theme information of respective theme routes in the theme route library.

Abstract: A layer stack including a first bonding dielectric material layer, a dielectric metal oxide layer, and a second bonding dielectric material layer is formed over a top surface of a substrate including a substrate semiconductor layer. A conductive material layer is formed by depositing a conductive material over the second bonding dielectric material layer. The substrate semiconductor layer is thinned by removing portions of the substrate semiconductor layer that are distal from the layer stack, whereby a remaining portion of the substrate semiconductor layer includes a top semiconductor layer. A semiconductor device may be formed on the top semiconductor layer.

Abstract: Disclosed are a control information sending method and detecting method, a base station, a terminal, and a computer storage medium. The method includes: a base station determining first-type physical layer control information, which is used for indicating a first-type control parameter of a second-type physical layer control channel; determining second-type physical layer control information, which is used for indicating a second-type control parameter of a data channel; sending the first-type physical layer control information; and sending the second-type physical layer control information on the second-type physical layer control channel.

Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes a stack of channel structures over a base structure. The semiconductor device structure also includes a first epitaxial structure and a second epitaxial structure sandwiching the channel structures. The semiconductor device structure further includes a gate stack wrapped around each of the channel structures and a backside conductive contact connected to the second epitaxial structure. A first portion of the backside conductive contact is directly below the base structure, and a second portion of the backside conductive contact extends upwards to approach a bottom surface of the second epitaxial structure. In addition, the semiconductor device structure includes an insulating spacer between a sidewall of the base structure and the backside conductive contact.

Abstract: A heat dissipation system of an electronic device including a body, a plurality of heat sources disposed in the body, and at least one centrifugal heat dissipation fan disposed in the body is provided. The centrifugal heat dissipation fan includes a housing and an impeller disposed in the housing on an axis. The housing has at least one inlet on the axis and has a plurality of outlets in different radial directions, and the plurality of outlets respectively correspond to the plurality of heat sources.

Abstract: An examination system is provided. The examination system includes an optical detector and analyzer. The optical detector emits a detection light source toward a target object and detects a respondent light which is induced from the target object in response to the detection light source to generate image data. The image data indicates a detection image. The analyzer receives the image data and determines which region of the target object the detection image belongs to according to the image data. When the analyzer determines that the detection image belongs to a specific region of the target object, the analyzer extracts at least one feature of the image data to serve as a basis for classification of the specific region.

Abstract: A method and apparatus for generating a drivable 3D character, an electronic device and a storage medium are disclosed, which relate to the field of artificial intelligence, such as computer vision, deep learning, or the like, and may be applied to 3D vision and other scenarios. The method may include: acquiring a 3D human body mesh model corresponding to a to-be-processed 2D image; performing a skeleton embedding operation on the 3D human body mesh model; and performing a skin binding operation on the 3D human body mesh model after the skeleton embedding operation to obtain a drivable 3D human body mesh model.

Abstract: The present application relates to the technical field of solar cells, and in particular, to a method for preparing a tunnel oxide layer and an amorphous silicon thin film and a TOPCon cell. The method includes sequentially depositing a tunnel oxide layer, an intrinsic amorphous silicon thin film and a doped amorphous silicon thin film at a deposition temperature of 440° C. to 460° C. by using a PECVD device. A flow rate of silane of depositing the intrinsic amorphous silicon thin film and the doped amorphous silicon thin film is in a range of 2000 sccm to 2500 sccm.

Abstract: A blackboard eraser cleaning device is provided and includes an outer shell (1). A cover (2) is arranged at the upper part of the outer shell (1), an inner shell (3) is arranged inside the outer shell (1). A clamping mechanism (19) is arranged at the upper end of the inner shell (3). A leaning station (8) is defined inside the clamping mechanism (19). A cylinder (9) is arranged around the clamping mechanism (19). A height adjustment mechanism (10) is arranged inside the outer shell (1). The height adjustment mechanism (10) includes a servo (101) arranged inside the outer shell (1) and located on a side of the inner shell (3). According to the present application, a variety of cleaning modes may be achieved to meet the actual usage of the blackboard eraser.

Abstract: A device includes a fin extending from a semiconductor substrate; a gate stack over the fin; a first spacer on a sidewall of the gate stack; a source/drain region in the fin adjacent the first spacer; an inter-layer dielectric layer (ILD) extending over the gate stack, the first spacer, and the source/drain region, the ILD having a first portion and a second portion, wherein the second portion of the ILD is closer to the gate stack than the first portion of the ILD; a contact plug extending through the ILD and contacting the source/drain region; a second spacer on a sidewall of the contact plug; and an air gap between the first spacer and the second spacer, wherein the first portion of the ILD extends across the air gap and physically contacts the second spacer, wherein the first portion of the ILD seals the air gap.

Abstract: Examples disclosed herein relate to device. The device includes a substrate, a plurality of adjacent pixel-defining layer (PDL structures disposed over the substrate, and a plurality of sub-pixels. The PDL structure have a top surface coupled to adjacent sidewalls of the PDL structure. The plurality of sub-pixels are defined by the PDL structures. Each sub-pixel includes an anode, an organic light emitting diode (OLED), a cathode, and an encapsulation layer. The organic light emitting diode (OLED) material disposed over the anode. The OLED material extends over the top surface of the PDL structure past the adjacent sidewalls. The cathode is disposed over the OLED material. The cathode extends over the top surface of the PDL structure past the adjacent sidewalls. The encapsulation layer is disposed over the cathode. The encapsulation layer has a first sidewall and a second sidewall.

Abstract: In some embodiments, the present disclosure relates to an integrated circuit (IC) in which a memory structure comprises an inhibition layer inserted between two ferroelectric layers to create a tetragonal-phase dominant ferroelectric structure. In some embodiments, the ferroelectric structure includes a first ferroelectric layer, a second ferroelectric layer overlying the first ferroelectric layer, and a first inhibition layer disposed between the first and second ferroelectric layers and bordering the second ferroelectric layer. The first inhibition layer is a different material than the first and second ferroelectric layers.

Abstract: A semiconductor device includes a first active region, a second active region and a dielectric wall. The second active region disposed adjacent to the first active region, and there is a first space between the first active region and the second active region. The dielectric wall is formed within the first space and has a first sidewall and a second sidewall opposite to the first sidewall. The first sidewall and the second sidewall opposite to the first sidewall continuously extend along a plane.