Patents by Inventor Hao Chuang

Hao Chuang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220200272
    Abstract: A transient voltage suppression device includes at least one diode string, a power clamp device, at least one first bypass diode, and at least two second bypass diodes. The diode string is coupled between a power terminal and a common bus and coupled to an input output (I/O) port. The power clamp device is coupled between the power terminal and the common bus. The first bypass diode is coupled between the common bus and a ground terminal The second bypass diodes are coupled in series, coupled between the common bus and the ground terminal, and coupled to the first bypass diode in reverse parallel. Alternatively, the first bypass diode and the second bypass diodes are replaced with at least one bi-directional electrostatic discharge (ESD) device.
    Type: Application
    Filed: December 23, 2020
    Publication date: June 23, 2022
    Applicant: AMAZING MICROELECTRONIC CORP.
    Inventors: Chih-Ting YEH, Sung-Chih HUANG, Che-Hao CHUANG
  • Publication number: 20220173140
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC comprises a first phase detection autofocus (PDAF) photodetector and a second PDAF photodetector in a substrate. A first electromagnetic radiation (EMR) diffuser is disposed along a back-side of the substrate and within a perimeter of the first PDAF photodetector. The first EMR diffuser is spaced a first distance from a first side of the first PDAF photodetector and a second distance less than the first distance from a second side of the first PDAF photodetector. A second EMR diffuser is disposed along the back-side of the substrate and within a perimeter of the second PDAF photodetector. The second EMR diffuser is spaced a third distance from a first side of the second PDAF photodetector and a fourth distance less than the third distance from a second side of the second PDAF photodetector.
    Type: Application
    Filed: February 1, 2022
    Publication date: June 2, 2022
    Inventors: Keng-Yu Chou, Chun-Hao Chuang, Kazuaki Hashimoto, Wei-Chieh Chiang, Cheng Yu Huang, Wen-Hau Wu, Chih-Kung Chang
  • Publication number: 20220165769
    Abstract: A method for forming an image sensor package is provided. An image sensor chip is formed over a package substrate. A protection layer is formed overlying the image sensor chip. The protection layer has a planar top surface and a bottom surface lining and contacting structures under the protection layer. An opening is formed into the protection layer and spaced around a periphery of the image sensor chip. A light shielding material is filled in the opening to form an on-wafer shield structure having a sidewall directly contact the protection layer.
    Type: Application
    Filed: February 10, 2022
    Publication date: May 26, 2022
    Inventors: Wen-Hau Wu, Chun-Hao Chuang, Kazuaki Hashimoto, Keng-Yu Chou, Wei-Chieh Chiang, Cheng Yu Huang
  • Patent number: 11329083
    Abstract: An image sensor package is provided. The image sensor package comprises a package substrate, and an image sensor chip arranged over the package substrate. The integrated circuit device further comprises a protection layer overlying the image sensor chip having a planar top surface and a bottom surface lining and contacting structures under the protection layer, and an on-wafer shield structure spaced around a periphery of the image sensor chip. The height of the image sensor package can be reduced since a discrete cover glass or an infrared filter and corresponding intervening materials are no longer needed since being replaced by the build in protection layer. The size of the image sensor package can be reduced since a discrete light shield and corresponding intervening materials are no longer needed since being replaced by the build in on wafer light shield structure.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: May 10, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Hau Wu, Chun-Hao Chuang, Kazuaki Hashimoto, Keng-Yu Chou, Wei-Chieh Chiang, Cheng Yu Huang
  • Publication number: 20220139983
    Abstract: In some embodiments, an image sensor is provided. The image sensor includes a photodetector disposed in a semiconductor substrate. A wave guide filter having a substantially planar upper surface is disposed over the photodetector. The wave guide filter includes a light filter disposed in a light filter grid structure. The light filter includes a first material that is translucent and has a first refractive index. The light filter grid structure includes a second material that is translucent and has a second refractive index less than the first refractive index.
    Type: Application
    Filed: January 19, 2022
    Publication date: May 5, 2022
    Inventors: Cheng Yu Huang, Chun-Hao Chuang, Chien-Hsien Tseng, Kazuaki Hashimoto, Keng-Yu Chou, Wei-Chieh Chiang, Wen-Chien Yu, Ting-Cheng Chang, Wen-Hau Wu, Chih-Kung Chang
  • Patent number: 11276716
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC comprises a first phase detection autofocus (PDAF) photodetector and a second PDAF photodetector in a substrate. A first electromagnetic radiation (EMR) diffuser is disposed along a back-side of the substrate and within a perimeter of the first PDAF photodetector. The first EMR diffuser is spaced a first distance from a first side of the first PDAF photodetector and a second distance less than the first distance from a second side of the first PDAF photodetector. A second EMR diffuser is disposed along the back-side of the substrate and within a perimeter of the second PDAF photodetector. The second EMR diffuser is spaced a third distance from a first side of the second PDAF photodetector and a fourth distance less than the third distance from a second side of the second PDAF photodetector.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: March 15, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Keng-Yu Chou, Chun-Hao Chuang, Kazuaki Hashimoto, Wei-Chieh Chiang, Cheng Yu Huang, Wen-Hau Wu, Chih-Kung Chang
  • Patent number: 11271099
    Abstract: A vertical bipolar transistor device is disclosed. The vertical bipolar transistor device includes a heavily-doped semiconductor substrate, a first semiconductor epitaxial layer, at least one first doped well, and an external conductor. The heavily-doped semiconductor substrate and the first doped well have a first conductivity type. The first semiconductor epitaxial layer has a second conductivity type. The first semiconductor epitaxial layer is formed on the heavily-doped semiconductor substrate. The first doped well is formed in the first semiconductor epitaxial layer. The external conductor is arranged outside the heavily-doped semiconductor substrate and the first semiconductor epitaxial layer and electrically connected to the heavily-doped semiconductor substrate and the first semiconductor epitaxial layer.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: March 8, 2022
    Assignee: Amazing Microelectronic Corp.
    Inventors: Chih-Ting Yeh, Sung-Chih Huang, Che-Hao Chuang
  • Publication number: 20220045410
    Abstract: The present disclosure relates to an oscillator apparatus comprising a differential transmission line forming a closed loop, a plurality of active core components that are electrically connected to the differential transmission line and that are configured to compensate for loss in the differential transmission line, a plurality of tuning elements that are electrically coupled with the differential transmission line, and a processor configured to control each tuning element of the plurality of tuning elements to activate or deactivate such that an effective electrical length of the differential transmission line is changed.
    Type: Application
    Filed: July 20, 2021
    Publication date: February 10, 2022
    Inventors: Tsung-Hao Chuang, Daquan Huang, Michael Chen, Shenggang Dong
  • Publication number: 20220045117
    Abstract: In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes an image sensor disposed within a first substrate. A first band-pass filter and a second band-pass filter are disposed on the first substrate. A dielectric structure is disposed on the first substrate. The dielectric structure is laterally between the first band-pass filter and the second band-pass filter and laterally abuts the first band-pass filter and the second band-pass filter.
    Type: Application
    Filed: October 21, 2021
    Publication date: February 10, 2022
    Inventors: Cheng Yu Huang, Chun-Hao Chuang, Chien-Hsien Tseng, Kazuaki Hashimoto, Keng-Yu Chou, Wei-Chieh Chiang, Wen-Hau Wu
  • Publication number: 20220037537
    Abstract: A vertical bipolar transistor device includes a heavily-doped semiconductor substrate, a first semiconductor epitaxial layer, at least one doped well, an isolation structure, and an external conductor. The heavily-doped semiconductor substrate and the doped well have a first conductivity type, and the first semiconductor epitaxial layer has a second conductivity type. The first semiconductor epitaxial layer is formed on the heavily-doped semiconductor substrate. The doped well is formed in the first semiconductor epitaxial layer. The isolation structure, formed in the heavily-doped semiconductor substrate and the first semiconductor epitaxial layer, surrounds the first semiconductor epitaxial layer and the at least one doped well. The external conductor is arranged outside the first semiconductor epitaxial layer and the doped well and electrically connected to the first semiconductor epitaxial layer and the doped well.
    Type: Application
    Filed: July 28, 2020
    Publication date: February 3, 2022
    Inventors: CHIH-TING YEH, SUNG-CHIH HUANG, CHE-HAO CHUANG
  • Publication number: 20220037512
    Abstract: A vertical bipolar transistor device is disclosed. The vertical bipolar transistor device includes a heavily-doped semiconductor substrate, a first semiconductor epitaxial layer, at least one first doped well, and an external conductor. The heavily-doped semiconductor substrate and the first doped well have a first conductivity type. The first semiconductor epitaxial layer has a second conductivity type. The first semiconductor epitaxial layer is formed on the heavily-doped semiconductor substrate. The first doped well is formed in the first semiconductor epitaxial layer. The external conductor is arranged outside the heavily-doped semiconductor substrate and the first semiconductor epitaxial layer and electrically connected to the heavily-doped semiconductor substrate and the first semiconductor epitaxial layer.
    Type: Application
    Filed: July 28, 2020
    Publication date: February 3, 2022
    Inventors: CHIH-TING YEH, SUNG-CHIH HUANG, CHE-HAO CHUANG
  • Patent number: 11233081
    Abstract: In some embodiments, an image sensor is provided. The image sensor includes a photodetector disposed in a semiconductor substrate. A wave guide filter having a substantially planar upper surface is disposed over the photodetector. The wave guide filter includes a light filter disposed in a light filter grid structure. The light filter includes a first material that is translucent and has a first refractive index. The light filter grid structure includes a second material that is translucent and has a second refractive index less than the first refractive index.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: January 25, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng Yu Huang, Chun-Hao Chuang, Chien-Hsien Tseng, Kazuaki Hashimoto, Keng-Yu Chou, Wei-Chieh Chiang, Wen-Chien Yu, Ting-Cheng Chang, Wen-Hau Wu, Chih-Kung Chang
  • Patent number: 11165929
    Abstract: An encrypted gallery management system and an implementation method thereof, comprising a management server and at least one information device, wherein the system converts one or more sets of corresponding time digital information into a time digital information totem and an encryption key totem, the time digital information totem and the encryption key totem are synthesized into an encrypted image. After user scans the encrypted image with his information device to obtain the totems, the information device can upload the totems to the management server for verification and comparison so that the management server is enabled to respond a specific service information to the information device so as to restrict the access of the information and thus prevent other unauthorized persons from obtaining the service information.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: November 2, 2021
    Inventor: Lien Hao Chuang
  • Publication number: 20210335359
    Abstract: A barrier-free intelligent voice system and a method for controlling thereof, wherein multiple words are recognized from a voice audio to create multiple independent semantic units. Meanwhile, the system can continuously determine whether they are one of multiple voice tags created by the user. Thereafter, a target object, a program command, and a remark corresponding to the voice tag can be determined based on the successfully compared voice tag combination. Accordingly, a corresponding program can be started or a remote device can be triggered to operate. The present disclosure can be regarded as an AI intelligent voice processing engine. By allowing users to define different types of voice tag combinations, it can eliminate the grammatical and semantic analysis of natural language processing, eliminate speech translation differences and errors between different languages, effectively reduce the amount of calculations, increase the processing speed of the system, minimize system judgment errors.
    Type: Application
    Filed: April 21, 2021
    Publication date: October 28, 2021
    Inventor: LIEN HAO CHUANG
  • Patent number: 11158662
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip has an image sensor within a substrate. A first dielectric has an upper surface that extends over a first side of the substrate and over one or more trenches within the first side of the substrate. The one or more trenches laterally surround the image sensor. An internal reflection structure arranged over the upper surface of the first dielectric. The internal reflection structure is configured to reflect radiation exiting from the substrate back into the substrate.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: October 26, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Keng-Yu Chou, Chun-Hao Chuang, Chien-Hsien Tseng, Kazuaki Hashimoto, Wei-Chieh Chiang, Cheng Yu Huang, Wen-Hau Wu, Chih-Kung Chang, Jhy-Jyi Sze
  • Patent number: 11158664
    Abstract: In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes a first image sensor disposed within a first substrate and a second image sensor disposed within a second substrate. The second substrate has a first side facing the first substrate. The first side includes angled surfaces defining one or more recesses within the first side. A band-pass filter is arranged between the first substrate and the second substrate and is configured to reflect electromagnetic radiation that is within a first range of wavelengths.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: October 26, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng Yu Huang, Chun-Hao Chuang, Chien-Hsien Tseng, Kazuaki Hashimoto, Keng-Yu Chou, Wei-Chieh Chiang, Wen-Hau Wu
  • Publication number: 20210288044
    Abstract: A floating base silicon controlled rectifier is provided, which at least comprises a first conductivity type layer; a second conductivity type well formed in the first conductivity type layer; a first conductivity type heavily doped region coupled to a first node and formed in the second conductivity type well; and a second conductivity type heavily doped region coupled to a second node and formed in the first conductivity type layer. The first conductivity type and the second conductivity type are opposite. When the first conductivity type is N type, the second conductivity type is P type. Alternatively, when the first conductivity type is P type, the second conductivity type is N type. By employing the proposed present invention, the floating base silicon controlled rectifier acts as a forward diode, and an input capacitance can be greatly reduced.
    Type: Application
    Filed: June 1, 2021
    Publication date: September 16, 2021
    Inventors: Chih-Ting YEH, Che-Hao CHUANG
  • Patent number: 11121159
    Abstract: A photo diode includes a pixel unit, a photo conversion layer, and a dielectric layer. The pixel unit includes a pair of pixels. The photo conversion layer is above the pixel unit and has a pair of portions, each of which corresponds to a respective one of the pixels. The dielectric layer is between the portions of the photo conversion layer. A method of manufacturing the photo diode is also disclosed.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: September 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Tzu-Jui Wang, Keng-Yu Chou, Chun-Hao Chuang, Ming-Chieh Hsu, Ren-Jie Lin, Jen-Cheng Liu, Dun-Nian Yaung
  • Publication number: 20210265414
    Abstract: A BSI image sensor includes a substrate including a front side and a back side opposite to the front side, a pixel sensor disposed in the substrate, and a color filter disposed over the pixel sensor. The pixel sensor includes a plurality of first micro structures disposed over the back side of the substrate. The color filter includes a plurality of second micro structures disposed over the back side of the substrate. The first micro structures are arranged symmetrically to a first axial, and the second micro structures are arranged symmetrically to a second axial.
    Type: Application
    Filed: May 7, 2021
    Publication date: August 26, 2021
    Inventors: WEI-CHIEH CHIANG, KENG-YU CHOU, CHUN-HAO CHUANG, WEN-HAU WU, JHY-JYI SZE, CHIEN-HSIEN TSENG, KAZUAKI HASHIMOTO
  • Patent number: D956770
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: July 5, 2022
    Inventor: Lien Hao Chuang