SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A manufacturing method of a semiconductor device includes the following steps. A first stacked structure and a second stacked structure are formed on a core region and an input/output (I/O) region of a semiconductor substrate respectively. The first stacked structure includes a first patterned oxide layer, a first patterned nitride layer, and a first dummy gate. The second stacked structure includes a second patterned oxide layer, a second patterned nitride layer, and a second dummy gate. The first dummy gate and the second dummy gate are removed for forming a first recess above the core region and a second recess above the I/O region. A first gate structure is formed in the first recess and a second gate structure is formed in the second recess. The first patterned nitride layer is removed before the step of forming the first gate structure in the first recess.
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device including a core region and an input/output region and a manufacturing method thereof.
2. Description of the Prior ArtIn the continuously improved semiconductor integrated circuit technology, the sizes of the semiconductor devices become smaller for increasing the integrity of the integrated circuit. In the scaling down process, the thickness control of layers in the semiconductor device becomes more and more critical. For improving the metal-oxide-semiconductor field effect transistor (MOSFET) device performance as feature sizes continue to decrease, the traditional gate oxide and polysilicon gate electrode are replaced by a high dielectric constant (high-k) gate dielectric and a metal gate electrode. In high-k gate stacks, the interfacial layer (IL) underlying the high-k dielectric layer plays a critical role in the performance of the MOSFET.
In an integrated circuit, different circuit modules and/or transistors and other devices in the same chip may operate indifferent voltage regimes. For instance, in an integrated switching-mode power supply, which may include a power transistor and a control circuit for switching the power transistor ON and OFF to convert a supply voltage into a desired output voltage, the power transistor may have an operating voltage much higher than an operating voltage of transistors constituting the control circuit. In order to have an area-efficient high voltage device with low voltage control devices fabricated on a same die, gate insulation layers with different thicknesses are required. However, the manufacturing process may become complicated and/or negative effects may be generated by the approaches of forming gate dielectric layers with different thicknesses, and the manufacturing yield may be influenced accordingly.
SUMMARY OF THE INVENTIONA semiconductor device and a manufacturing method are provided in the present invention. Stacked structures including a patterned oxide layer and a patterned nitride layer are formed on a core region and an input/output (I/O) region, and the patterned nitride layer on the core region is removed after a step of removing dummy gates and before a step of forming gate structures for forming a thinner dielectric layer on the core region. By the manufacturing method of the present invention, it is not necessary to remove the oxide dielectric layer on the core region, and influence of an oxide dielectric layer etching process on other oxide portion may be avoided. The manufacturing yield may be enhanced and the electric performance of the semiconductor device may be improved accordingly.
According to an embodiment of the present invention, a manufacturing method of a semiconductor device is provided. The manufacturing method includes the following steps. A semiconductor substrate is provided first. The semiconductor substrate includes a core region and an input/output (I/O) region defined thereon. A first stacked structure is formed on the core region. A second stacked structure is formed on the I/O region. The first stacked structure includes a first patterned oxide layer, a first patterned nitride layer, and a first dummy gate. The first patterned nitride layer is formed on the first patterned oxide layer. The first dummy gate is formed on the first patterned nitride layer. The second stacked structure includes a second patterned oxide layer, a second patterned nitride layer, and a second dummy gate. The second patterned nitride layer is formed on the second patterned oxide layer. The second dummy gate is formed on the second patterned nitride layer. The first dummy gate and the second dummy gate are removed for forming a first recess above the core region and a second recess above the I/O region. A first gate structure is formed in the first recess, and a second gate structure is formed in the second recess. The first patterned nitride layer is removed before the step of forming the first gate structure in the first recess.
According to another embodiment of the present invention, a semiconductor device is provided. The semiconductor device includes a semiconductor substrate, a first gate structure, a second gate structure, an oxide dielectric layer, and a nitride dielectric layer. The semiconductor substrate includes a core region and an input/output (I/O) region defined thereon. The first gate structure is disposed on the core region. The second gate structure is disposed on the I/O region. The oxide dielectric layer is party disposed between the first gate structure and the semiconductor substrate and partly disposed between the second gate structure and the semiconductor substrate. The nitride dielectric layer is disposed between the second gate structure and the oxide dielectric layer.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
Please refer to
As shown in
For example, as shown in
In some embodiments, the oxide dielectric layer 21 may be formed by an oxidation treatment performed to the semiconductor substrate 10, such as a part of the fin structure 10F which is not covered by the shallow trench isolation 11, and the oxide dielectric layer 21 may include silicon oxide or other suitable oxide dielectric materials. The oxidation treatment mentioned above may include in-situ steam generation (ISSG) oxidation treatment or other appropriate oxidation treatments. Additionally, the nitride dielectric layer 22 may include silicon nitride or other suitable nitride dielectric materials. The method of forming the nitride dielectric layer 22 may include a chemical vapor deposition (CVD) process, such as an atomic layer deposition (ALD), or other suitable thin film processes. The material of the dummy gate material layer 23 may include amorphous silicon or other materials having higher etching selectivity to the nitride dielectric layer 22 for avoiding damaging the nitride dielectric layer 22 in the process of removing the first dummy gate 23A and the second dummy gate 23B subsequently, and the material of the cap layer 24 may include silicon nitride, silicon oxynitride, or other appropriate insulation materials, but not limited thereto.
It is worth noting that the material composition and the manufacturing method of the first stacked structure S1 and the second stacked structure S2 in the present invention are not limited to the condition described above. When the first stacked structure S1 and the second stacked structure S2 are formed by the manufacturing method described above, the thickness of the first patterned oxide layer 21A may be substantially equal to the thickness of the second patterned oxide layer 21B, and the thickness of the first patterned nitride layer 22A may be substantially equal to the thickness of the second patterned nitride layer 22B. In the subsequent processes, the first patterned nitride layer 22A on the core region R1 will be removed, and only the first patterned oxide layer 21A is used as an interfacial layer (IL) on the core region R1. The interfacial layer on the I/O region R2 is composed of the second patterned nitride layer 22B and the second patterned oxide layer 21B for high voltage semiconductor units formed on the I/O region R2. Therefore, the thickness of the nitride dielectric layer 22 may be modified according to the requirements of the high voltage semiconductor units formed on the I/O region R2, and the nitride dielectric layer is thicker than the oxide dielectric layer 21 generally, but not limited thereto.
As shown in
As shown in
As shown in
In some embodiments, the material of the first high-k dielectric layer 51A and the material of the second high-k dielectric layer 51B may include hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), tantalum oxide (Ta2O5) , zirconium oxide (ZrO2) , or other suitable high-k dielectric materials. The material of the first work function layer 52A and the material of the second work function layer 52B may include tantalum nitride (TaN), titanium nitride (TiN), titanium carbide (TiC), titanium aluminide (TiAl), titanium aluminum carbide (TiAlC), or other suitable N type work function materials and/or P type work function materials. The first metal gate 53A and the second metal gate 53B may include a low resistivity metal, such as aluminum (Al), tungsten (W), copper (Cu), titanium aluminide, or other appropriate low resistivity metals. In some embodiments, the first high-k dielectric layer 51A and the second high-k dielectric layer 51B may be formed by the same process and the same material layer, the first metal gate 53A and the second metal gate 53B may be formed by the same process and the same material layer, and the material of the first work function layer 52A may be identical to or different from the material of the second work function layer 52B according to other considerations, but not limited thereto. Because the first patterned nitride layer on the core region R1 is removed before the step of forming the first gate structure GS1 and the second patterned nitride layer 22B is not removed, the first patterned oxide layer 21A on the core region R1 may directly contact the first high-k dielectric layer 51A of the first gate structure GS1, and the second patterned nitride layer 22B maybe located between the second high-k dielectric layer 51B of the second gate structure GS2 and the second patterned oxide layer 21B. A semiconductor device 100 shown in
As shown in
In addition, the oxide dielectric layer 21 disposed between the first gate structure GS1 and the semiconductor substrate 10 may be regarded as the first patterned oxide layer 21A, and the oxide dielectric layer 21 disposed between the second gate structure GS2 and the semiconductor substrate 10 may be regarded as the second patterned oxide layer 21B. Accordingly, the material of the first patterned oxide layer 21A on the core region R1 may be identical to the material of the second patterned oxide layer 21B on the I/O region R2, and the thickness of the first patterned oxide layer 21A on the core region R1 may be equal to the thickness of the second patterned oxide layer 21B on the I/O region R2. The first patterned oxide layer 21A does not have to be removed before the step of forming the first gate structure GS1 and the second gate structure GS2 for reforming a required interfacial layer because the first patterned oxide layer 21A corresponding to the first gate structure GS1 on the core region R1 and the second patterned oxide layer 21B corresponding to the second gate structure GS2 on the I/O region R2 may be formed by the same process, and the interfacial layer corresponding to the second gate structure GS2 may be composed of the second patterned oxide layer 21B and the second patterned nitride layer 22B disposed on the second patterned oxide layer 21B. The damage to the oxidation layer 40 and the interlayer dielectric 33 during the process of removing the first patterned oxide layer 21A may be avoided accordingly, and the purposes of enhancing manufacturing yield and improving the electrical performance may be achieved.
In some embodiments, the first gate structure GS1 may include the first high-k dielectric layer 51A and the first metal gate 53A, and the second gate structure GS2 may include the second high-k dielectric layer 51B and the second metal gate 53B. The first metal gate 53A is disposed on the first high-k dielectric layer 51A, and the second metal gate 53B is disposed on the second high-k dielectric layer 51B. In a cross-sectional view of the semiconductor device 100 (such as
To summarize the above descriptions, in the semiconductor device and the manufacturing method thereof according to the present invention, the stacked structures including the patterned oxide layer and the patterned nitride layer are formed on the core region and the I/O region, and the patterned nitride layer on the core region is removed after the step of removing the dummy gates and before the step of forming the gate structures for forming the thinner dielectric layer on the core region. By the manufacturing method of the present invention, it is not necessary to remove the oxide dielectric layer on the core region, and the damage to other oxide portion, such as the oxidation layer and the interlayer dielectric, by the etching process for removing the oxide dielectric layer may be avoided. The condition of controlling the critical dimension (CD) of the gate structure on the core region and the height of the interlayer dielectric may be improved. The manufacturing yield may be enhanced and the electric performance of the semiconductor device may be improved accordingly.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Claims
1. A manufacturing method of a semiconductor device, comprising:
- providing a semiconductor substrate comprising a core region and an input/output (I/O) region defined thereon;
- forming a first stacked structure on the core region, wherein the first stacked structure comprises: a first patterned oxide layer; a first patterned nitride layer formed on the first patterned oxide layer; and a first dummy gate formed on the first patterned nitride layer;
- forming a second stacked structure on the I/O region, wherein the second stacked structure comprises: a second patterned oxide layer; a second patterned nitride layer formed on the second patterned oxide layer; and a second dummy gate formed on the second patterned nitride layer;
- removing the first dummy gate and the second dummy gate for forming a first recess above the core region and a second recess above the I/O region;
- forming a spacer on a sidewall of the first stacked structure and a sidewall of the second stacked structure before the step of removing the first dummy gate and the second dummy gate, wherein the first recess and the second recess are surrounded by the spacer, an oxidation layer is formed on a surface of the spacer by the step of removing the first dummy gate and the second dummy gate, and the first recess and the second recess are surrounded by the oxidation layer;
- forming a first gate structure in the first recess;
- forming a second gate structure in the second recess; and
- removing the first patterned nitride layer before the step of forming the first gate structure in the first recess.
2. The manufacturing method of the semiconductor device according to claim 1, wherein the first patterned oxide layer and the second patterned oxide layer are formed by the same process patterning an oxide dielectric layer.
3. The manufacturing method of the semiconductor device according to claim 1, wherein the first patterned nitride layer and the second patterned nitride layer are formed by the same process patterning a nitride dielectric layer.
4. (canceled)
5. (canceled)
6. The manufacturing method of the semiconductor device according to claim 1, wherein the oxidation layer is formed before the step of removing the first patterned nitride layer.
7. The manufacturing method of the semiconductor device according to claim 1, wherein the first gate structure comprises:
- a first high dielectric constant (high-k) dielectric layer; and
- a first metal gate formed on the first high-k dielectric layer, wherein the first high-k dielectric layer comprises a U-shaped structure surrounding the first metal gate.
8. The manufacturing method of the semiconductor device according to claim 7, wherein the first patterned oxide layer directly contacts the first high-k dielectric layer.
9. The manufacturing method of the semiconductor device according to claim 1, wherein the second gate structure comprises:
- a second high-k dielectric layer; and
- a second metal gate formed on the second high-k dielectric layer, wherein the second high-k dielectric layer comprises a U-shaped structure surrounding the second metal gate.
10. The manufacturing method of the semiconductor device according to claim 9, wherein the second nitride layer is located between the second high-k dielectric layer and the second patterned oxide layer.
11. A semiconductor device comprising:
- a semiconductor substrate comprising a core region and an input/output (I/O) region defined thereon;
- a first gate structure disposed on the core region, wherein the first gate structure comprises: a first high dielectric constant (high-k) dielectric layer; and a first metal gate disposed on the first high-k dielectric layer, wherein the first high-k dielectric layer comprises a U-shaped structure surrounding the first metal gate in a cross-sectional view of the semiconductor device;
- a second gate structure disposed on the I/O region, wherein the second gate structure comprises: a second high-k dielectric layer; and a second metal gate disposed on the second high-k dielectric layer, wherein the second high-k dielectric layer comprises a U-shaped structure surrounding the second metal gate in a cross-sectional view of the semiconductor device;
- an oxide dielectric layer party disposed between the first gate structure and the semiconductor substrate and partly disposed between the second gate structure and the semiconductor substrate, wherein the oxide dielectric layer disposed between the first gate structure and the semiconductor substrate directly contacts the first high-k dielectric layer; and
- a nitride dielectric layer disposed between the second gate structure and the oxide dielectric layer, wherein the nitride dielectric layer is disposed between the second high-k dielectric layer and the oxide dielectric layer, and the nitride dielectric layer directly contacts the second high-k dielectric layer.
12-15. (canceled)
16. The semiconductor device according to claim 11, further comprising:
- a spacer disposed on a sidewall of the first gate structure, a sidewall of the second gate structure, a sidewall of the oxide dielectric layer, and a sidewall of the nitride dielectric layer.
17. The semiconductor device according to claim 16, further comprising:
- an oxidation layer partly disposed between the spacer and the first gate structure and partly disposed between the spacer and the second gate structure.
18. The semiconductor device according to claim 11, wherein the nitride dielectric layer is thicker than the oxide dielectric layer.
Type: Application
Filed: Dec 11, 2017
Publication Date: May 9, 2019
Inventors: Hao-Hsuan Chang (Kaohsiung City), Yao-Hsien Chung (Kaohsiung City), Fu-Yu Tsai (Tainan City)
Application Number: 15/838,243