Patents by Inventor Hao-I Yang
Hao-I Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190004915Abstract: An exemplary testing environment can operate in a testing mode of operation to test whether a memory device or other electronic devices communicatively coupled to the memory device operate as expected or unexpectedly as a result of one or more manufacturing faults. The testing mode of operation includes a shift mode of operation, a capture mode of operation, and/or a scan mode of operation. In the shift mode of operation and the scan mode of operation, the exemplary testing environment delivers a serial input sequence of data to the memory device. In the capture mode of operation, the exemplary testing environment delivers a parallel input sequence of data to the memory device.Type: ApplicationFiled: September 11, 2017Publication date: January 3, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming-Hung CHANG, Atul KATOCH, Chia-En HUANG, Ching-Wei WU, Donald G. MIKAN, JR., Hao-I YANG, Kao-Cheng LIN, Ming-Chien TSAI, Saman M.I ADHAM, Tsung-Yung CHANG, Uppu Sharath CHANDRA
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Publication number: 20180342291Abstract: A sense amplify enable (SAE) signal is generated on a SAE line by receiving a trigger signal at a first circuit portion coupled to a first domain power supply and a second circuit portion coupled to a second domain power supply. The second domain power supply is separate and distinct from the first domain power supply. The first circuit portion and the second circuit portion are each further coupled to the SAE line for carrying the SAE signal. For a first period of time, a first portion of the SAE signal is generated based on the first domain power supply using the first circuit portion. And, for second period of time, a second portion of the SAE signal is generated based on the second domain power supply using a second circuit portion.Type: ApplicationFiled: January 3, 2018Publication date: November 29, 2018Inventors: Fu-An Wu, Cheng Hung Lee, Chen-Lin Yang, Hao-I Yang, Tsung-Hsien Huang
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Patent number: 10121520Abstract: A memory array includes a first column of memory cells, a second column of memory cells, a first pre-charge circuit, a second pre-charge circuit and a set of input output circuits. The first column of memory cells includes a first bit line, a first word line and a first bit line bar. The second column of memory cells includes the first bit line bar, a second word line and a second bit line. The first pre-charge circuit is coupled to the first bit line. The second pre-charge circuit is coupled to the first bit line bar. The first column of memory cells and the second column of memory cells are configured to share the first bit line bar. The first bit line and the first bit line bar are in a first plane. At least a portion of the first word line and at least a portion of the second word line are in a second plane intersecting the first plane.Type: GrantFiled: April 24, 2018Date of Patent: November 6, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Hao Hu, Yi-Tzu Chen, Hao-I Yang, Cheng-Jen Chang, Geng-Cing Lin
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Publication number: 20180240505Abstract: A memory array includes a first column of memory cells, a second column of memory cells, a first pre-charge circuit, a second pre-charge circuit and a set of input output circuits. The first column of memory cells includes a first bit line, a first word line and a first bit line bar. The second column of memory cells includes the first bit line bar, a second word line and a second bit line. The first pre-charge circuit is coupled to the first bit line. The second pre-charge circuit is coupled to the first bit line bar. The first column of memory cells and the second column of memory cells are configured to share the first bit line bar. The first bit line and the first bit line bar are in a first plane. At least a portion of the first word line and at least a portion of the second word line are in a second plane intersecting the first plane.Type: ApplicationFiled: April 24, 2018Publication date: August 23, 2018Inventors: Yu-Hao HU, Yi-Tzu CHEN, Hao-I YANG, Cheng-Jen CHANG, Geng-Cing LIN
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Patent number: 9959911Abstract: A memory array includes a first column of memory cells, a second column of memory cells and a set of switching elements. The first column of memory cells includes a first bit line, a first word line and a second bit line. The second column of memory cells includes the second bit line, a second word line and a third bit line. The first and second column of memory cells are configured to share the second bit line. The first and second bit lines are in a first plane. At least a portion of the first word line and at least a portion of the second word line are in a second plane intersecting the first plane. An amount of bit line switching elements in the set of bit line switching elements is equal to N*2, where N is an amount of columns of memory cells in the memory array.Type: GrantFiled: February 27, 2017Date of Patent: May 1, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Hao Hu, Yi-Tzu Chen, Hao-I Yang, Cheng-Jen Chang, Geng-Cing Lin
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Patent number: 9934845Abstract: A semiconductor device comprising a first supply voltage, a second supply voltage, different from the first supply voltage; and a switching circuit. The switching circuit comprises an input configured to receive an input signal corresponding to the first supply voltage and an output configured to output an output signal corresponding to the second supply voltage. The switching circuit is a combined latch with a built-in level shifter that provides latching functionality and level shifting functionality and a leakage path is cut-off when the switching circuit is providing latching functionality.Type: GrantFiled: January 13, 2017Date of Patent: April 3, 2018Assignee: Taiwan Semiconductor Manufacturing Campany LimitedInventors: Hao-I Yang, Cheng Hung Lee, Chi-Kai Hsieh, Fu-An Wu, Tsung-Hsien Huang
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Publication number: 20170345487Abstract: A semiconductor device comprising a first supply voltage, a second supply voltage, different from the first supply voltage; and a switching circuit. The switching circuit comprises an input configured to receive an input signal corresponding to the first supply voltage and an output configured to output an output signal corresponding to the second supply voltage. The switching circuit is a combined latch with a built-in level shifter that provides latching functionality and level shifting functionality and a leakage path is cut-off when the switching circuit is providing latching functionality.Type: ApplicationFiled: January 13, 2017Publication date: November 30, 2017Inventors: Hao-I Yang, Cheng Hung Lee, Chi-Kai Hsieh, Fu-An Wu, Tsung-Hsien Huang
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Patent number: 9721651Abstract: A circuit includes: a first data line; a second data line; a write driver including first and second transistors; a first switch connected in series with the first transistor to form a first series-connected pair; a second switch in series with the second transistor to form a second series-connected pair; and a level shifter which includes the first and second transistors. The first series-connected pair is coupled between a first voltage node and the first data line. The second series-connected pair is coupled between the first voltage node and the second data line. Gate terminals of the first and second transistors are correspondingly cross-coupled with the second and first data lines.Type: GrantFiled: September 30, 2016Date of Patent: August 1, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hao-I Yang, Chia-En Huang, Cheng Hung Lee, Geng-Cing Lin, Jung-Ping Yang
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Patent number: 9711209Abstract: A semiconductor memory includes a first layer including at least a first memory cell, a second layer including at least a second memory cell, and a wordline shared by the first memory cell and the second memory cell. The first and second memory cells can be above or below the wordline and be coupled to different bit lines.Type: GrantFiled: March 16, 2016Date of Patent: July 18, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hao-I Yang, Yi-Tzu Chen, Cheng-Jen Chang, Geng-Cing Lin, Yu-Hao Hu
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Publication number: 20170169864Abstract: A memory array includes a first column of memory cells, a second column of memory cells and a set of switching elements. The first column of memory cells includes a first bit line, a first word line and a second bit line. The second column of memory cells includes the second bit line, a second word line and a third bit line. The first and second column of memory cells are configured to share the second bit line. The first and second bit lines are in a first plane. At least a portion of the first word line and at least a portion of the second word line are in a second plane intersecting the first plane. An amount of bit line switching elements in the set of bit line switching elements is equal to N*2, where N is an amount of columns of memory cells in the memory array.Type: ApplicationFiled: February 27, 2017Publication date: June 15, 2017Inventors: Yu-Hao HU, Yi-Tzu CHEN, Hao-I YANG, Cheng-Jen CHANG, Geng-Cing LIN
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Patent number: 9583494Abstract: A memory array includes a first memory column having a first bit line, a first word line and a second bit line. The memory array also includes a second memory column having the second bit line, a second word line and a third bit line. The first memory column and the second memory column are configured to share the second bit line. The sharing of the second bit line facilitates sharing one or more memory array components between the first memory column and the second memory column.Type: GrantFiled: October 23, 2013Date of Patent: February 28, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Hao Hu, Yi-Tzu Chen, Hao-I Yang, Cheng-Jen Chang, Geng-Cing Lin
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Publication number: 20170018303Abstract: A circuit includes: a first data line; a second data line; a write driver including first and second transistors; a first switch connected in series with the first transistor to form a first series-connected pair; a second switch in series with the second transistor to form a second series-connected pair; and a level shifter which includes the first and second transistors. The first series-connected pair is coupled between a first voltage node and the first data line. The second series-connected pair is coupled between the first voltage node and the second data line. Gate terminals of the first and second transistors are correspondingly cross-coupled with the second and first data lines.Type: ApplicationFiled: September 30, 2016Publication date: January 19, 2017Inventors: Hao-I YANG, Chia-En HUANG, Cheng Hung LEE, Geng-Cing LIN, Jung-Ping YANG
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Patent number: 9484084Abstract: A circuit includes a first data line, a second data line, a first pulling device, a second pulling device, a third pulling device, and a fourth pulling device. The first pulling device is configured to be activated or deactivated responsive to a first control signal; and is configured to pull a first signal at the first data line toward a voltage level of a first voltage based on a second signal at the second data line when the first pulling device is activated. The second pulling device is configured to be activated or deactivated responsive to a second control signal; and is configured to pull the second signal at the second data line toward the voltage level of the first voltage based on the first signal at the first data line when the second pulling device is activated.Type: GrantFiled: October 22, 2015Date of Patent: November 1, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hao-I Yang, Chia-En Huang, Cheng Hung Lee, Geng-Cing Lin, Jung-Ping Yang
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Publication number: 20160240245Abstract: A circuit includes a first data line, a second data line, a first pulling device, a second pulling device, a third pulling device, and a fourth pulling device. The first pulling device is configured to be activated or deactivated responsive to a first control signal; and is configured to pull a first signal at the first data line toward a voltage level of a first voltage based on a second signal at the second data line when the first pulling device is activated. The second pulling device is configured to be activated or deactivated responsive to a second control signal; and is configured to pull the second signal at the second data line toward the voltage level of the first voltage based on the first signal at the first data line when the second pulling device is activated.Type: ApplicationFiled: October 22, 2015Publication date: August 18, 2016Inventors: Hao-I YANG, Chia-En HUANG, Cheng Hung LEE, Geng-Cing LIN, Jung-Ping YANG
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Publication number: 20160211010Abstract: A semiconductor memory includes a first layer including at least a first memory cell, a second layer including at least a second memory cell, and a wordline shared by the first memory cell and the second memory cell. The first and second memory cells can be above or below the wordline and be coupled to different bit lines.Type: ApplicationFiled: March 16, 2016Publication date: July 21, 2016Inventors: Hao-I YANG, Yi-Tzu Chen, Cheng-Jen Chang, Geng-Cing Lin, Yu-Hao Hu
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Patent number: 9299391Abstract: A three dimensional (3D) circuit includes a first layer including at least a first memory cell, a second layer including at least a second memory cell, and a wordline shared by the first memory cell and the second memory cell. The first and second memory cells can be adjacent memory cells or bit cells coupled to different bit lines.Type: GrantFiled: January 21, 2014Date of Patent: March 29, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hao-I Yang, Yi-Tzu Chen, Cheng-Jen Chang, Geng-Cing Lin, Yu-Hao Hu
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Publication number: 20150206555Abstract: A three dimensional (3D) circuit includes a first layer including at least a first memory cell, a second layer including at least a second memory cell, and a wordline shared by the first memory cell and the second memory cell. The first and second memory cells can be adjacent memory cells or bit cells coupled to different bit lines.Type: ApplicationFiled: January 21, 2014Publication date: July 23, 2015Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hao-I YANG, Yi-Tzu CHEN, Cheng-Jen CHANG, Geng-Cing LIN, Yu-Hao HU
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Publication number: 20150109847Abstract: A memory array includes a first memory column having a first bit line, a first word line and a second bit line. The memory array also includes a second memory column having the second bit line, a second word line and a third bit line. The first memory column and the second memory column are configured to share the second bit line. The sharing of the second bit line facilitates sharing one or more memory array components between the first memory column and the second memory column.Type: ApplicationFiled: October 23, 2013Publication date: April 23, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Hao HU, Yi-Tzu CHEN, Hao-I YANG, Cheng-Jen CHANG, Geng-Cing LIN
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Patent number: 8958237Abstract: An apparatus and method for executing a write operation in a static random access memory (SRAM) array including memory cells that are coupled to a plurality of word lines and to a plurality of bit lines are provided. A clock signal is generated to start a write operation. A pulse is generated on the plurality of word lines in response to the clock signal. An operation voltage of the SRAM array is lowered for a period of time during the write operation. The period of time is controlled and the pulse is ended using a tracking circuit. The tracking circuit includes a plurality of tracking memory cells. The plurality of tracking memory cells have a timing characteristic that emulates a timing characteristic of the SRAM array during the write operation. The tracking circuit controls the period of time and ends the pulse based on the emulated timing characteristic.Type: GrantFiled: November 13, 2013Date of Patent: February 17, 2015Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Hao-I Yang, Yi-Tzu Chen, Cheng-Jen Chang, Geng-Cing Lin, Yu-Hao Hu, Chia-Hao Hsu
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Patent number: 8854897Abstract: A static random access memory apparatus and a bit-line voltage controller includes a controller, a pull-up circuit, a pull-down circuit and a voltage keeping circuit. The controller receives a bank selecting signal and a clock signal, and decides a pull-up time period, a pull-down time period and a voltage keeping time period according to the bank selecting signal and the clock signal. The pull-up circuit pulls up a bit-line power according to a first reference voltage within the pull-up time period. The pull-down circuit pulls down the bit-line power according to a second reference voltage within the pull-down time period. The voltage keeping circuit keeps the bit-line power to equal to an output voltage during the voltage keeping time period. The voltage keeping time period is after the pull-up time period and the pull-down time period.Type: GrantFiled: November 1, 2012Date of Patent: October 7, 2014Assignees: Faraday Technology Corp., National Chiao Tung UniversityInventors: Ching-Te Chuang, Nan-Chun Lien, Wei-Nan Liao, Chi-Hsin Chang, Hao-I Yang, Wei Hwang, Ming-Hsien Tu