Abstract: An electronic transformer includes a first forward rectifier, a second forward rectifier, a third forward rectifier and a backward rectifier. The first forward rectifier is coupled between a first-phase power and a first output terminal. The second forward rectifier is coupled between a second-phase power and the first output terminal. The third forward rectifier is coupled between a third-phase power and the first output terminal. The backward rectifier is coupled between a neutral line and a second output terminal. The first forward rectifier, the second forward rectifier, and the third forward rectifier are configured to half-wave rectify the first-phase power, the second-phase power, and the third-phase power to generate rectified first-phase to third-phase power sources, and superimpose the rectified first-phase to third-phase power sources on the first output end to serve as an output voltage of the electronic transformer.

Abstract: A method includes placing a plurality of package components over a carrier, encapsulating the plurality of package components in an encapsulant, forming a light-sensitive dielectric layer over the plurality of package components and the encapsulant, exposing the light-sensitive dielectric layer using a lithography mask, and developing the light-sensitive dielectric layer to form a plurality of openings. Conductive features of the plurality of package components are exposed through the plurality of openings. The method further includes forming redistribution lines extending into the openings. One of the redistribution lines has a length greater than about 26 mm. The redistribution lines, the plurality of package components, the encapsulant in combination form a reconstructed wafer.

Abstract: A memory controller for use in a data storage device is provided. A low-density parity check (LDPC) process performed by the memory controller includes an initial phase, a decoding phase, and an output phase. The memory controller includes a variable-node circuit and a check-node circuit. During the initial phase, the variable-node circuit performs the following steps: obtaining a channel value, that is read from a flash memory, from a channel-value memory; transmitting the channel value to the check-node circuit to calculate a syndrome; and in response to the syndrome not being 0, setting a value of a register corresponding to each entry of a plurality of entries in a variable-node memory, and entering the decoding phase.

Abstract: Exemplary methods of packaging a substrate may include rotationally aligning a substrate to a predetermined angular position. The methods may include transferring the substrate to a metrology station. The methods may include measuring a topology of the substrate at the metrology station. The methods may include applying a first chucking force to the substrate to flatten the substrate. The methods may include generating a mapping of a die pattern on an exposed surface of the substrate. The methods may include transferring the substrate to a printing station. The methods may include applying a second chucking force to the substrate to flatten the substrate against a surface of the printing station. The methods may include adjusting a printing pattern based on the mapping of the die pattern. The methods may include printing the printing pattern on the exposed surface of the substrate.

Abstract: A multi-piece wheel rim includes a first component made of carbon fiber and having a plurality of slots; dissimilar material members made of a material other than carbon fiber and respectively fixed into the slots, each dissimilar member having plasticity and a tapped hole; threaded bushings engaging respectively and threadedly the tapped holes of the dissimilar material members; a second component; and headed screws extending through the second component and respectively engaging threadedly the threaded bushings, thereby fastening the second component to the first component. A method is hereby disclosed for fastening together components of the multi-piece wheel rim.

Abstract: A memory controller, for use in a data storage device, is provided. A low-density parity-check (LDPC) decoding procedure performed by the memory controller includes an initial phase, a decoding phase, and an output phase in sequence. The memory controller includes a memory-index control circuit and a decoder. The decoder includes a decoding pipeline to perform the decoding phase of the LDPC decoding procedure. After the data storage device is booted up, the decoder reads a plurality of first codewords from a variable-node memory using a first order via the memory-index control circuit for LDPC decoding. In response to the decoder determining that a specific codeword among the first codewords has decoding failure, the decoder is reset to read a plurality of second codewords from the variable-node memory using a second order via the memory-index control circuit for LDPC decoding. The first order is different from the second order.

Abstract: A wheel includes a spoke having a mounting hole that extends in a radial direction, and a blind hole that extends in an axial direction and that is in spatial communication with the mounting hole. The wheel includes a rim having a second through hole that is aligned with the mounting hole. The wheel further includes a connecting unit connecting the spoke with the rim. The connecting unit includes a rod extending through the through hole into the mounting hole and having an engaging hole that is aligned with the blind hole. The connecting unit further includes a fastener extending through the blind hole into the engaging hole and engaging with the engaging hole.

Abstract: A MEMS structure is provided. The MEMS structure includes a substrate and a backplate, the substrate has an opening portion, and the backplate is disposed on one side of the substrate and has acoustic holes. The MEMS structure also includes a diaphragm disposed between the substrate and the backplate, and the diaphragm extends across the opening portion of the substrate and includes outer ventilation holes and inner ventilation holes arranged in a concentric manner. The outer ventilation holes and the inner ventilation holes are relatively arranged in a ring shape and surround the center of the diaphragm. The MEMS structure further includes a pillar disposed between the backplate and the diaphragm. The pillar prevents the diaphragm from being electrically connected to the backplate.

Abstract: A backlight module and an electronic device are provided. The backlight module, having a main region and a peripheral region near the main region, includes a light conversion layer, multiple light conversion patterns located in the peripheral region, and multiple light emitting units emitting a light beam. A first portion and a second portion of the light beam emitted respectively from the main region and the peripheral region both have at least one corresponding position in a CIE 1931 color space. One among the at least one corresponding position of the first portion of the light beam has corresponding coordinates (x1, y1). One among the at least one corresponding position of the second portion of the light beam has corresponding coordinates (x2, y2). The corresponding coordinates (x1, y1) and the corresponding coordinates (x2, y2) satisfy the following relation: 0?|x1?x2|?0.2.

Abstract: A physical unclonable function (PUF) generator including a substrate and semiconductor units is provided. Each of the semiconductor units includes an isolation structure, a first conductive line, and a second conductive line. The isolation structure is located in the substrate. The isolation structure has a first protrusion portion and a recess. The first protrusion portion and the recess are adjacent to each other. The first conductive line is located above the first protrusion portion and the recess. The second conductive line is located above the first conductive line. At least one short circuit randomly exists between at least one of the first conductive lines and at least one of the second conductive lines in at least one of the semiconductor units.

Abstract: The invention relates to an apparatus and a method for generating a Low-Density Parity-Check (LDPC) code. The apparatus includes: a LDPC encoder, a look-ahead circuitry and an exclusive-OR (XOR) calculation circuitry. The LDPC encoder is arranged operably to encode a front part of a user data using a 2-stage encoding algorithm with a parity check matrix to generate a first calculation result. The look-ahead circuitry is arranged operably to perform a dot product operation on a rear part of the user data and one of a plurality of feature rows corresponding to the parity check matrix to generate a second calculation result in each iteration. The XOR calculation circuitry is arranged operably to perform an XOR operation on the first calculation result and the second calculation result to generate a front part of the LDPC code.

Abstract: The invention relates to a method and an apparatus for decoding a Low-Density Parity-Check (LDPC) code. The method includes the following steps, which is performed by an LDPC decoder including a variable-node calculation circuitry and a check-node calculation circuitry: A first-stage state entering when a codeword has been stored in a static random access memory (SRAM) is detected. The check-node calculation circuitry is arranged operably to perform a modulo 2 multiplication on the codeword and a parity check matrix to calculate a plurality of first syndromes in the first-stage state. A second-stage state is entered when the first syndromes indicate that the codeword obtained in the first-stage state is incorrect. The variable-node calculation circuitry is arranged operably to perform a bit flipping algorithm accordingly to generate variable nodes, and calculate second soft bits for the variable nodes in the second-stage state.

Abstract: A semiconductor device includes a die, an encapsulant over a front-side surface of the die, a redistribution structure on the encapsulant, a thermal module coupled to the back-side surface of the die, and a bolt extending through the redistribution structure and the thermal module. The die includes a chamfered corner. The bolt is adjacent to the chamfered corner.

Abstract: A semiconductor device has a top metal layer, a first passivation layer over the top metal layer, a first redistribution layer over the first passivation layer, a first polymer layer, and a first conductive via extending through the first polymer layer. The first polymer layer is in physical contact with the first passivation layer.

Abstract: The present disclosure provides a system and method for determining condition of wafers during processing of the wafers. The system and method include detecting vibrations of a wafer transfer robot, generating signals based upon the vibrations, and processing the signals for determining a condition of the wafers held by the wafer transfer robot.

Abstract: An electronic device and a method for manufacturing the same are provided. The electronic device includes: a substrate; an electronic component disposed on the substrate; a first optical component disposed on the substrate and the electronic component; and a first optical adhesive disposed between the substrate and the first optical component to bond the substrate and the first optical component, wherein a Young's modulus of the first optical adhesive ranges between 10 kPa and 150 kPa.

Abstract: A method includes the following steps. A seed layer is formed over a structure having at least one semiconductor die. A first patterned photoresist layer is formed over the seed layer, wherein the first patterned photoresist layer includes a first opening exposing a portion of the seed layer. A metallic wiring is formed in the first opening and on the exposed portion of the seed layer. A second patterned photoresist layer is formed on the first patterned photoresist layer and covers the metallic wiring, wherein the second patterned photoresist layer includes a second opening exposing a portion of the metallic wiring. A conductive via is formed in the second opening and on the exposed portion of the metallic wiring. The first patterned photoresist layer and the second patterned photoresist layer are removed. The metallic wiring and the conductive via are laterally wrapped around with an encapsulant.

Abstract: A semiconductor package includes a first die; a first redistribution structure over the first die, the first redistribution structure being conterminous with the first die; a second die over the first die, a first portion of the first die extending beyond a lateral extent of the second die; a conductive pillar over the first portion of the first die and laterally adjacent to the second die, the conductive pillar electrically coupled to first die; a molding material around the first die, the second die, and the conductive pillar; and a second redistribution structure over the molding material, the second redistribution structure electrically coupled to the conductive pillar and the second die.

Abstract: A thin-film-deposition machine includes a chamber, a carrier, an extraction ring and a dispensing unit. The chamber includes a containing space and an extraction channel disposed around the containing space. The extraction channel is partitioned into a first, a second and a third channel areas. The carrier is disposed within the containing space. The first channel area is connected to the third channel area via the second channel area. The third channel area is formed with a height greater than that of the first channel area. The extraction ring includes a plurality of extraction holes and a ring channel. The extraction holes are disposed around the carrier for extracting gas from the containing space to the extraction channel, sequentially via the extraction holes, the ring channel. Thereby an even and steady flow field can be formed above the carrier and the thickness uniformity of film deposition can be improved.

Abstract: A semiconductor structure includes a semiconductor wafer, a first surface mount component, a second surface mount component and a first barrier structure. The first surface mount component is disposed on the semiconductor wafer, and electrically connected to the semiconductor wafer through a plurality of first electrical connectors. The second surface mount component is disposed on the semiconductor wafer, and electrically connected to the semiconductor wafer through a plurality of second electrical connectors, wherein an edge of the second surface mount component is overhanging a periphery of the semiconductor wafer. The first barrier structure is disposed on the semiconductor wafer in between the second electrical connectors and the edge of the second surface mount component, wherein a first surface of the first barrier structure is facing the second electrical connectors, and a second surface of the first barrier structure is facing away from the second electrical connectors.