Abstract: A package structure including an interposer, a semiconductor die, through insulator vias, an insulating encapsulant and a redistribution layer is provided. The interposer includes a core structure having a first and second surface, first metal layers disposed on the first and second surface, second metal layers disposed on the second surface over the first metal layers, and third metal layers disposed on the second surface over the second metal layers. The semiconductor die is disposed on the interposer. The through insulator vias are disposed on the interposer and electrically connected to the plurality of first metal layers. The insulating encapsulant is disposed on the interposer over the first surface and encapsulating the semiconductor die and the plurality of through insulator vias. The redistribution layer is disposed on the insulating encapsulant and electrically connected to the semiconductor die and the plurality of through insulator vias.

Abstract: A heat dissipation system of a portable electronic device is provided. The heat dissipation system includes a body and at least one fan. A heat source of the portable electronic device is disposed in the body. The fan is a centrifugal fan disposed in the body. The fan has at least one flow inlet, at least one flow outlet, and at least one spacing portion. The flow outlet faces toward the heat source, and the spacing portion surrounds the flow inlet and abuts against the body, so as to isolate the flow inlet and the heat source in two spaces independent of each other in the body.

Abstract: A surface treatment and an apparatus for semiconductor packaging are provided. A surface of a conductive layer is treated to create a roughened surface. In one example, nanowires are formed on a surface of the conductive layer. In the case of a copper conductive layer, the nanowires may include a CuO layer. In another example, a complex compound is formed on a surface of the conductive layer. The complex compound may be formed using, for example, thiol and trimethyl phosphite.

Abstract: A MEMS structure is provided. The MEMS structure includes a substrate having an opening portion and a backplate disposed on one side of the substrate and having acoustic holes. The MEMS structure also includes a diaphragm disposed between the substrate and the backplate and extending across the opening portion of the substrate. The diaphragm includes a ventilation hole, and an air gap is formed between the diaphragm and the backplate. The MEMS structure further includes a filler structure disposed on the diaphragm, and a portion of the filler structure is disposed in the ventilation hole.

Abstract: A semiconductor device includes a first plurality of dies encapsulated by an encapsulant, an interposer over the first plurality of dies, an interconnect structure over and electrically connected to the interposer, and a plurality of conductive pads on a surface of the interconnect structure opposite the interposer. The interposer includes a plurality of embedded passive components. Each die of the first plurality of dies is electrically connected to the interposer. The interconnect structure includes a solenoid inductor in a metallization layer of the interconnect structure.

Abstract: A chip package including a first semiconductor die, a support structure and a second semiconductor die is provided. The first semiconductor die includes a first dielectric layer and a plurality of conductive vias, the first dielectric layer includes a first region and a second region, the conductive vias is embedded in the first region of the first dielectric layer; a plurality of conductive pillars is disposed on and electrically connected to the conductive vias. The second semiconductor die is stacked over the support structure and the second region of the first dielectric layer; and an insulating encapsulant encapsulates the first semiconductor die, the second semiconductor die, the support structure and the conductive pillars, wherein the second semiconductor die is electrically connected to the first semiconductor die through the conductive pillars.

Abstract: Actual physical locations of dies on a substrate package may be identified without using a full metrology scan of the substrate. Instead, one or more cameras may be used to efficiently locate the approximate location of any of the alignment features based on their expected positioning in the design file for the packages are substrate. The cameras may then be moved to locations where alignment features should be, and images may be captured to determine the actual location of the alignment feature. These actual locations of the alignment features may then be used to identify coordinates for the dies, as well as rotations and/or varying heights of the dies on the packages. A difference between the expected location from the design file and the actual physical location may be used to adjust instructions for the digital lithography system to compensate for the misalignment of the dies.

Abstract: A method of forming a flash memory cell includes the following steps. A first dielectric layer and a floating gate layer are deposited on a substrate sequentially. Three blocking structures having oblique sidewalls broaden from bottom to top penetrating through the first dielectric layer and the floating gate layer are formed. A first part and a second part of the floating gate layer between two adjacent blocking structures are etched respectively, so that a first floating gate having two sharp top corners and oblique sidewalls, and a second floating gate having two sharp top corners and oblique sidewalls, are formed. The three blocking structures are removed. A first isolating layer and a first selective gate covering the first floating gate are formed and a second isolating layer and a second selective gate covering the second floating gate are formed. A flash memory cell formed by said method is also provided.

Abstract: A package structure includes a bottom plate, a semiconductor package, a top plate, a screw and an anti-loosening coating. The semiconductor package is disposed over the bottom plate. The top plate is disposed over the semiconductor package, and includes an internal thread in a screw hole of the top plate. The screw penetrates through the bottom plate, the semiconductor package and the top plate, and includes an external thread. The external thread of the screw is engaged to the internal thread of the top plate, and the anti-loosening coating is adhered between the external thread and the internal thread.

Abstract: A semiconductor package includes a redistribution structure, at least one semiconductor device, a heat dissipation component, and an encapsulating material. The at least one semiconductor device is disposed on and electrically connected to the redistribution structure. The heat dissipation component is disposed on the redistribution structure and includes a concave portion for receiving the at least one semiconductor device and an extending portion connected to the concave portion and contacting the redistribution structure, wherein the concave portion contacts the at least one semiconductor device. The encapsulating material is disposed over the redistribution structure, wherein the encapsulating material fills the concave portion and encapsulates the at least one semiconductor device.

Abstract: An atomic layer deposition apparatus for coating particles is disclosed. The atomic layer deposition apparatus includes a vacuum chamber, a shaft sealing device, and a driving unit. The driving unit is connected to and drives the vacuum chamber to rotate through the shaft sealing device. The vacuum chamber includes a reaction space for accommodating a plurality of particles, wherein the reaction space has a polygonal columnar shape or a wavy circular columnar shape. An air extraction line and an air intake line are fluidly connected to the vacuum chamber, and the air intake line is used to transport a precursor gas and a non-reactive gas to the reaction space. Through the special shape of the reaction space together with the non-reactive gas, the particles in the reaction space can be effectively stirred to form a thin film with a uniform thickness on the surface of each particle.

Abstract: The disclosure provides a method for fabricating a semiconductor structure with strengthened patterns. The method includes forming a masking layer on the substrate, the masking layer including a peripheral region and an array region adjacent to the peripheral region; forming a first etched peripheral pattern in the peripheral region and a first etched array pattern in the array region, wherein the first etched peripheral pattern and the first etched array pattern have a top surface, a sidewall and a bottom surface, the sidewall connecting the top surface to the bottom surface; forming a second peripheral pattern on the first etched peripheral pattern and forming a second array pattern on the first etched array pattern; and etching the masking layer using the first etched peripheral pattern and the second peripheral pattern as an etching mask to form an etched masking layer in the peripheral region.

Abstract: A driving circuit, a driving method and a display apparatus are provided. The driving method is provided for driving a light-emitting unit including a first light-emitting element series and a second light-emitting element series connected in parallel and connected to a processing unit and a driving unit of a driving circuit. The processing unit detects a first voltage value and a second voltage value. The driving unit detects and transmits a first current value and a second current value to the processing unit. The processing unit determines and compares a first power value and a second power value. When the first and second power values are different, the processing unit controls the driving unit to adjust a driving current setting of the light-emitting element series until the first and second power values are equal. The invention ensures luminance consistency of different light-emitting element series and the luminance uniformity of display apparatus.

Abstract: The present disclosure provides a multi-substrate handling system having an alignment apparatus capable of positioning each of a set of substrates in predetermined orientations for transfer. A buffer chamber is configured to receive and condition the set of substrates which are disposed on a substrate carrier. A first transfer assembly is configured to transfer the set of substrates to and from the buffer chamber and is capable of transferring each of the set of substrates from the alignment apparatus to the carrier in the buffer chamber. The carrier includes a plurality of modules capable of securing the set of substrates. The system includes a second transfer assembly having at least two robots configured to transfer the carrier of the set of substrates between the buffer chamber and a process chamber. The process chamber is capable of processing the set of substrates using different process parameters for each substrate.

Abstract: A method for fabricating a physically unclonable function (PUF) device includes the steps of first defining a PUF cell region on a substrate and then performing a process to form a defect on the PUF cell region. Preferably, the formation of the defect could be accomplished by forming a shallow trench isolation (STI) on the substrate, forming a gate material layer on the substrate and the STI, patterning the gate material layer to form a first gate material layer and a second gate material layer, and then forming an epitaxial layer between and connecting the first gate material layer and the second gate material layer.

Abstract: A semiconductor structure includes a first die, a first encapsulant, a second die and a second encapsulant. The first die includes a first dielectric layer and first conductive pads in the first dielectric layer. The first encapsulant laterally encapsulates and is in direct contact with the first dielectric layer of the first die. The second die includes a second dielectric layer and second conductive pads in the second dielectric layer. The second encapsulant laterally encapsulates and is in direct contact with the second dielectric layer of the second die. The first conductive pads of the first die are in physical contact with a first portion of the second conductive pads of the second die.

Abstract: A package includes a first and a second package component. The first package component includes a first metal trace and a second metal trace at the surface of the first package component. The second metal trace is parallel to the first metal trace. The second metal trace includes a narrow metal trace portion having a first width, and a wide metal trace portion having a second width greater than the first width connected to the narrow metal trace portion. The second package component is over the first package component. The second package component includes a metal bump overlapping a portion of the first metal trace, and a conductive connection bonding the metal bump to the first metal trace. The conductive connection contacts a top surface and sidewalls of the first metal trace. The metal bump is neighboring the narrow metal trace portion.

Abstract: The present disclosure relates to an integrated chip structure having a first substrate including a plurality of transistor devices disposed within a semiconductor material. An interposer substrate includes vias extending through a silicon layer. A copper bump is disposed between the first substrate and the interposer substrate. The copper bump has a sidewall defining a recess. Solder is disposed over the copper bump and continuously extending from over the copper bump to within the recess. A conductive layer is disposed between the first substrate and the interposer substrate and is separated from the copper bump by the solder.

Abstract: A chip package structure includes an interposer structure that contains a package-side redistribution structure, an interposer core assembly, and a die-side redistribution structure. The interposer core assembly includes at least one silicon substrate interposer, and each of the at least one silicon substrate interposer includes a respective silicon substrate, a respective set of through-silicon via (TSV) structures vertically extending through the respective silicon substrate, a respective set of interconnect-level dielectric layers embedding a respective set of metal interconnect structures, and a respective set of metal bonding structures that are electrically connected to the die-side redistribution structure. The chip package structure includes at least two semiconductor dies that are attached to the die-side redistribution structure, and an epoxy molding compound (EMC) multi-die frame that laterally encloses the at least two semiconductor dies.

Abstract: A backlight module and an electronic device are provided. The backlight module, having a main region and a peripheral region near the main region, includes a light conversion layer, multiple light conversion patterns located in the peripheral region, and multiple light emitting units emitting a light beam. A first portion and a second portion of the light beam emitted respectively from the main region and the peripheral region both have at least one corresponding position in a CIE 1931 color space. One among the at least one corresponding position of the first portion of the light beam has corresponding coordinates (x1, y1). One among the at least one corresponding position of the second portion of the light beam has corresponding coordinates (x2, y2). The corresponding coordinates (x1, y1) and the corresponding coordinates (x2, y2) satisfy the following relation: 0?|x1?x2|?0.2.