Abstract: A method and associated memory system for operating a memory controller. The method reads the data from the memory using a progression of hard reads of the data; utilizes in the progression a set of hard read retry entries including at least a first hard read retry entry and a second hard read retry entry, each of the hard reads performed with a different hard read bias based on the set of the hard read retry entries; continues the progression until a successful read occurs or for a predetermined number times of unsuccessful hard reads; records a read bias used for the successful read and checksums of all unsuccessful hard reads; and after the successful read, replaces the first hard read retry entry with the read-bias of the successful read.

Abstract: A method of fabricating a high energy density bonded magnet is provided. The method includes combining a critical rare earth free magnetic material with a polymeric material to obtain a mixture. The method further includes extruding the mixture, and compression molding the extruded mixture to obtain a compression molded product. The critical rare earth free magnetic material may include Sm2Fe17N3 (Sm—Fe—N) in a content of at least 95 wt. %. The polymeric material may include one or more of a polyamide, a polycarbonate, a polyphenylene sulfide, a polyether ether ketone, a polyurethane, a polytetrafluoroethylene, a thermoplastic elastomer, a polyvinyl chloride, and polyethylene. A high energy density bonded magnet formed by the method is also provided. The high energy density bonded magnet may have a maximum energy product (BHmax) of at least 20 MGOe.

Abstract: A method and memory system for estimating parameters for reading data from a memory. The method determines respective counts of memory cell read patterns obtained by reading pages of the data from the memory with corresponding pre-determined read thresholds, wherein for a NAND PV state, two thresholds (RT1 and RT2) are obtained according to used page read thresholds; determines corresponding survival function values (SF1 and SF2); uses the two read thresholds (RT1 and RT2) and the corresponding survival function values (SF1 and SF2) to determine a mean ? and a standard deviation ? of a NAND PV state; and infers a soft read interval ? and LLR values through a deep neural network (DNN) that takes, as an input, parameters (?1, ?1) and (?2, ?2) corresponding to respective means and standard deviations of two adjacent PV states having a read valley in between.

Abstract: A method and memory system for estimating parameters for reading data from a memory having a plurality of NAND program-voltage (PV) states. The method determines respective counts of memory cell read patterns obtained by reading pages of the data from the memory with corresponding pre-determined read thresholds, wherein for a NAND PV state, three thresholds (RT1, RT2, RT3) are obtained according to used page read thresholds; uses the at least three read thresholds (RT1, RT2, RT3) and the corresponding survival function values (SF1, SF2, SF3) to determine parametric values for a PV distribution of at least one NAND PV state; and utilizes at least one deep neural network (DNN) to infer a center read threshold between two of the NAND PV states, a soft read interval ?, and LLR values, where the DNN takes, as input, the parametric values for the PV distribution of the least one NAND PV state.

Abstract: Devices, systems, and methods for improving the performance of a non-volatile memory are described. An example method includes extracting one or more parameters from each of multiple history reads of a page of the memory device, and processing, using each of multiple first neural networks, a corresponding history read of the multiple history reads to generate a corresponding intermediate vector of multiple intermediate vectors. Each of the multiple first neural networks are trained using measurements from one or more pages of another memory device, and each first neural network is activated upon determining that the one or more parameters for the corresponding history read have been extracted. The method further includes processing, using a second neural network, the multiple intermediate vectors to generate an updated read threshold set, and applying the updated read threshold set to the memory device to retrieve information from the memory device.

Abstract: A memory system and associated method for calculating a voltage threshold for reading data from the memory system. The memory system including a memory device including multiple pages in a memory region and a controller coupled to the memory device. The controller is configured to: perform at least one read operation on the memory device including reading of the multiple pages in a memory region of the memory device to obtain program voltage state distributions across the multiple pages; generate a synthetic model of the program voltage state distributions of the memory device based on the at least one read operation; and calculate from the synthetic model at least one voltage threshold between two of the program voltage state distributions.

Abstract: Devices, systems, and methods for improving the performance of a non-volatile memory are described. An example method includes extracting one or more parameters from each of multiple history reads of a page of the memory device, and processing, using each of multiple first neural networks, a corresponding history read of the multiple history reads to generate a corresponding intermediate vector of multiple intermediate vectors. Each of the multiple first neural networks are trained using measurements from one or more pages of another memory device, and each first neural network is activated upon determining that the one or more parameters for the corresponding history read have been extracted. The method further includes processing, using a second neural network, the multiple intermediate vectors to generate an updated read threshold set, and applying the updated read threshold set to the memory device to retrieve information from the memory device.

Abstract: Devices, systems, and methods for improving performance of an iterative decoder in a non-volatile memory are described. An example method includes obtaining a hard error percentage, a spare byte percentage, and a total error count associated with a first page in the memory device, determining that the total error count is greater than a threshold value that is determined based on the hard error percentage and the spare byte percentage, and performing, based on the determining, a data relocation operation that relocates at least some data from the first page to a second page different from the first page.

Abstract: Techniques related to improving the error correction performance of a bit-flipping (BF) decoder for decoding a codeword using one or more trellis decoders are described. In some examples, the BF decoder can identify a set of unsatisfied check nodes among a set of check nodes that can be decoded using a trellis decoder. The trellis decoder can perform trellis decoding on the set of unsatisfied check nodes and variable nodes connected to the set of unsatisfied check nodes to determine bit values of the variable nodes to resolve the set of unsatisfied check nodes identified by the BF decoding. The BF decoder can use the bit values of the variable nodes determined by the trellis decoding in a next iteration of the BF decoding to decode the codeword.

Abstract: Devices, systems and methods for improving performance of a memory device are described. An example method includes obtaining a plurality of samples corresponding to a probability distribution for each of a plurality of cell voltage distributions of the memory device, each of the plurality of cell voltage distributions corresponding to a read voltage, determining, based on the samples obtained for the plurality of cell voltage distributions, a number of first deep neural networks (DNNs), estimating, for each of the first DNNs, one or more parameters of the corresponding probability distribution based on the plurality of samples, training, based on the samples and the corresponding one or more parameters, each of the first DNNs, and training, based on the samples and the one or more parameters from each of the first DNNs, a second DNN to enable generation of an updated read voltage value for retrieving information from the memory device.

Abstract: A memory device of a storage device may receive a garbage collection command from a memory controller coupled to the memory device to perform an internal garbage collection operation within the memory device. The memory device may attempt to perform the garbage collection operation to internally move valid memory pages from a first memory block to a second memory block to free up the first memory block in response to the garbage collection command. The memory device may send an acknowledgement to the memory controller for the garbage collection command.

Abstract: A memory system and a method for generation of log likelihood ratio LLR values. The system has a storage medium having therein a processor, and a memory controller of the memory system configured to send a soft read command to the storage medium. The processor in the storage medium, in response to the soft read command, is configured to read pages of data stored in the storage medium and generate within the storage medium the LLR values.

Abstract: Devices, systems, and methods for improving performance of a memory device are described. An example method includes extracting parameters, which include a read threshold set, from each of a first set of host reads, replacing, based on the parameters, at least one host read from a second set of host reads by at least one host read from the first set of host reads, using a deep neural network (DNN) to generate an updated read threshold set, wherein an input to the DNN comprises the parameters from each of the second set of host reads subsequent to the replacing, and applying the updated read threshold set to the memory device to retrieve information from the memory device. In an example, the number of the first set of host reads is at least two orders of magnitude greater than the number of the second set of host reads.

Abstract: A memory device of a storage device may receive a garbage collection command from a memory controller coupled to the memory device to perform an internal garbage collection operation within the memory device. The memory device may attempt to perform the garbage collection operation to internally move valid memory pages from a first memory block to a second memory block to free up the first memory block in response to the garbage collection command. The memory device may send an acknowledgement to the memory controller for the garbage collection command.

Abstract: A scheme for encoding and decoding a codeword into which address information is embedded. A write operation for this scheme includes generating tagging information including address information; encoding user information, meta information, the tagging information and additional shortened bits to generate parity information; generating a codeword including the user information, the meta information and the parity information; and storing the codeword in a memory device.

Abstract: The present invention relates to a hinged quick installation fence, comprising at least two fence piece units and a ground inserting rod, the fence piece unit includes at least two fence pieces and a connecting hinge, the fence pieces are rotatably connected together by the connecting hinge, and the leftmost fence piece is provided with a left hinge member, the rightmost fence piece is provided with a right hinge member, the adjacent fence piece units are connected in pairs correspondingly through the left hinge member and the right hinge member, and the ground inserting rod is inserted into the left hinge member and the right hinge member and fixed, and the fence piece units form a fence for use. The advantageous effects of the present invention are as following: the hinged quick installation fence can be transported, installed and stored more conveniently by combining two or more fence pieces into a fence piece unit, thereby saving manpower and time costs.

Abstract: Devices, systems, and methods for improving performance of a memory device are described. An example method includes extracting parameters, which include a read threshold set, from each of a first set of host reads, replacing, based on the parameters, at least one host read from a second set of host reads by at least one host read from the first set of host reads, using a deep neural network (DNN) to generate an updated read threshold set, wherein an input to the DNN comprises the parameters from each of the second set of host reads subsequent to the replacing, and applying the updated read threshold set to the memory device to retrieve information from the memory device. In an example, the number of the first set of host reads is at least two orders of magnitude greater than the number of the second set of host reads.

Abstract: Techniques for adjusting log likelihood ratios in a decoder may include determining an assist read (AR) zone based on performing assist reads (AR) of multibit memory cells of a memory. Soft reads of the multibit memory cells may be performed to determine a bin within the AR zone for each bit of the data stored in the memory cells. Each bin is associated with a log likelihood ratio (LLR) value. Error correction decoding on the data stored in the memory cells may be performed followed by collecting statistics on the decoded data for each bin in each AR zone. A hard error percentage may be computed for each AR zone based on the collected statistics, and one or more LLR values may be adjusted based on the hard error percentage.

Abstract: Techniques for adjusting log likelihood ratios in a decoder may include determining an assist read (AR) zone based on performing assist reads (AR) of multibit memory cells of a memory. Soft reads of the multibit memory cells may be performed to determine a bin within the AR zone for each bit of the data stored in the memory cells. Each bin is associated with a log likelihood ratio (LLR) value. Error correction decoding on the data stored in the memory cells may be performed followed by collecting statistics on the decoded data for each bin in each AR zone. A hard error percentage may be computed for each AR zone based on the collected statistics, and one or more LLR values may be adjusted based on the hard error percentage.

Abstract: A scheme for encoding and decoding a codeword into which address information is embedded. A write operation for this scheme includes generating tagging information including address information; encoding user information, meta information, the tagging information and additional shortened bits to generate parity information; generating a codeword including the user information, the meta information and the parity information; and storing the codeword in a memory device.