Abstract: Memory controllers bit-flipping (BF) decoders and methods that selectively apply a checksum-aided error reduction (CA-ER) scheme to BF decoding of a low-density parity-check (LDPC) code. In decoding a codeword, a hard decision value resulting from decoding a select variable node is changed when a first condition is satisfied to yield an updated hard decision value. Also, when the first condition is satisfied, a current checksum value after processing the select variable node is updated using the updated hard decision value. The CA-ER scheme is applied when the updated checksum value is not reduced to a set minimum and a second condition based on a previous checksum value, calculated after a previous variable node is processed, is satisfied.

Abstract: Techniques related to methods and systems for improving a performance related to reading data stored in memory cells. The method includes selecting a first voltage read range and a second voltage read range from multiple voltage read ranges that are associated with a number of bits storable in a memory cell. The method includes receiving, a first set of parameters that represent a first probability distribution of first candidate voltage read thresholds within the first voltage read range. The method includes receiving a second set of parameters that represent a second probability distribution of second candidate voltage read thresholds within the second voltage read range. The method includes generating, based on an input to an objective function, a voltage read threshold. The method includes reading data stored in the memory cell based on the voltage read threshold.

Abstract: A controller estimates optimal read threshold values for a memory device using deep learning. The memory device includes multiple pages coupled to select word lines in a memory region. The controller performs multiple read operations on a select type of page for each word line using multiple read threshold sets, obtains fail bit count (FBC) information associated with each read operation, and determines an optimal read threshold set for each word line based on the FBC information. When optimal read threshold sets for the select word lines are different each other, the controller predicts a best read threshold set using the optimal read threshold sets.

Abstract: A controller optimizes read threshold values for a memory device using domain transformation. The controller determines, for the decoded data of each read operation, an asymmetric ratio (AR) and the number of unsatisfied checks (USCs), the AR indicating a ratio of the number of a first binary value to the number of a second binary value in the decoded data. The controller determines a Z-axis such that AR values of the threshold sets are arranged in a set order along the Z-axis. The controller determines an optimum read threshold set using coordinate values on the Z-axis, which correspond to a set AR value and a set USC value.

Abstract: A memory controller optimizes read threshold values for a memory device using multi-dimensional search. The controller performs a read operation on cells using a pair of default read threshold values on a multi-dimensional plane. When the read operation has failed, the controller determines program states of cells and a pair of next read threshold values based on the program states and performs an additional read operation using the next read threshold values.

Abstract: Devices, systems and methods for reducing complexity of a bit-flipping decoder for quasi-cyclic (QC) low-density parity-check (LDPC) codes are described. An example method includes receiving a noisy codeword that is based on a transmitted codeword generated from an irregular QC-LDPC code, the irregular QC-LDPC code having an associated parity matrix, storing, based on a weight of a plurality of columns of the parity matrix of the irregular QC-LDPC code, a portion of the noisy codeword corresponding to the plurality of columns in a first buffer of a plurality of buffers, and accessing and processing the portion of the noisy codeword that includes applying a vertically shuffled scheduling (VSS) scheme that uses a plurality of processing units to determine a candidate version of a portion of the transmitted codeword that corresponds to the portion of the noisy codeword.

Abstract: Multiple memory systems with respective decoders employ a low latency implementation of a read recovery level feature in decoding data. The decoding comprises receiving from a host a read request for decoding read data at a first recovery level by a first memory system, a first decoder of the first memory system being set at a second recovery level with a corresponding maximum iteration number when the read request is received by the first memory system; and operating the first decoder, after a set time elapses, to decode the read data at the second recovery level. A second decoder of a second memory system is set at the first recovery level for at least part of the time during which the first decoder operates to decode the read data at the second recovery level.

Abstract: Devices, systems, and methods for dynamic control of a quasi-cyclic low-density parity-check (QC-LDPC) bit-flipping decoder are described. An example method includes receiving a noisy codeword based on a transmitted codeword generated from an irregular QC-LDPC code, performing a plurality of decoding iterations on the received noisy codeword, each of the plurality of decoding iterations comprising processing of N circulant matrices, performing, before processing a current circulant matrix in a current M-th iteration of the plurality of decoding iterations, operations that include computing a number of bit flips that have occurred over the processing of N previous circulant matrices, the N previous circulant matrices spanning the current M-th iteration and an (M?1)-th iteration, wherein M and N are positive integers, and wherein M?2, and updating, based on the number of bit flips, a bit-flipping threshold, and processing, based on the updated bit-flipping threshold, the current circulant matrix.

Abstract: A descrambler receives data from a memory device. The descrambler calculates a sub-syndrome weight for multiple bits in each of the plurality of descrambled sequences using a set parity check matrix to generate multiple sub-syndrome weights, one for each of the plurality of descrambled sequences. The descrambler selects a sub-syndrome weight among the multiple sub-syndrome weights. The descrambler determines, as a correct scrambler sequence for descrambling the data, a scrambler sequence corresponding to the selected sub-syndrome weight, among the plurality of scrambler sequences.

Abstract: Disclosed are devices, systems and methods for improving a bit-flipping algorithm for an irregular LDPC code in a non-volatile memory device. An example method includes receiving a noisy codeword, the codeword having been generated from an irregular low-density parity-check code, performing a first iteration of a bit-flipping algorithm on the noisy codeword, computing a first syndrome based on an output codeword of the first iteration, determining that the first syndrome comprises a non-zero vector and no bits of the noisy codeword were flipped during the first iteration of the bit-flipping algorithm, flipping, based on the determining, at least one bit of the output codeword, the at least one bit corresponding to a variable node of the plurality of variable nodes with a smallest column weight connected to one or more unsatisfied check nodes of the plurality of check nodes, and computing, subsequent to the flipping, a second syndrome.

Abstract: Embodiments describe a method for reading data from storage that includes selecting a block of memory to read, identifying a read retry table for reading the block, determining that the read retry table for the selected block of memory needs to be updated, and reading the block of memory using a new set of read threshold voltages from the read retry table. Responsive to a successful read operation using the new set of voltages, the method can also include replacing the initial set of read voltages in the first field with the new set of read voltages, and filling the plurality of subsequent fields in the read retry table with additional sets of read threshold voltages identified from a read retry neighbor table, where at least one of the additional sets of read voltages is closest in distance to the initial set of read voltages in read voltage space.

Abstract: Techniques are described for improving the decoding latency and throughput of an error correction system that includes a bit flipping (BF) decoder, where the BF decoder uses a bit flipping procedure. In an example, different decoding parameters are determined including any of a decoding number of a decoding iteration, a checksum of a codeword, a degree of a variable node, and a bit flipping threshold defined for the bit flipping procedure. Based on one or more of these decoding parameters, a decision can be generated to skip the bit flipping decoding procedure, thereby decreasing the decoding latency and increasing the decoding throughput. Otherwise, the bit flipping decoding procedure can be performed to compute a bit flipping energy and determine whether particular bits are to be flipped or not. Hence, the overall performance (e.g., bit error rate) is not significantly impacted.

Abstract: A memory controller optimizes read threshold values for a memory device using multi-dimensional search. The controller performs a read operation on cells using a pair of default read threshold values on a multi-dimensional plane. When the read operation has failed, the controller determines program states of cells and a pair of next read threshold values based on the program states and performs an additional read operation using the next read threshold values.

Abstract: Techniques are described for improving the decoding latency and throughput of an error correction system that includes a bit flipping (BF) decoder, where the BF decoder uses a bit flipping procedure. In an example, different decoding parameters are determined including any of a decoding number of a decoding iteration, a checksum of a codeword, a degree of a variable node, and a bit flipping threshold defined for the bit flipping procedure. Based on one or more of these decoding parameters, a decision can be generated to skip the bit flipping decoding procedure, thereby decreasing the decoding latency and increasing the decoding throughput. Otherwise, the bit flipping decoding procedure can be performed to compute a bit flipping energy and determine whether particular bits are to be flipped or not. Hence, the overall performance (e.g., bit error rate) is not significantly impacted.

Abstract: Multiple memory systems with respective decoders employ a low latency implementation of a read recovery level feature in decoding data. The decoding comprises receiving from a host a read request for decoding read data at a first recovery level by a first memory system, a first decoder of the first memory system being set at a second recovery level with a corresponding maximum iteration number when the read request is received by the first memory system; and operating the first decoder, after a set time elapses, to decode the read data at the second recovery level. A second decoder of a second memory system is set at the first recovery level for at least part of the time during which the first decoder operates to decode the read data at the second recovery level.

Abstract: A memory system includes a memory device including memory sets and a controller including a decoder. The decoder receives multiple codewords from the memory sets and decodes the multiple codewords. The decoder determines an inter-set delay for a codeword of a select memory set. When the inter-set delay is greater than a maximum inter-set delay, the decoder determines a total decoding time based on an effective inter-set delay and an effective decoding time. The decoder outputs the decoded codeword at the end of the total decoding time.

Abstract: A memory system includes a memory device including memory sets and a controller including a decoder. The decoder receives multiple codewords from the memory sets and decodes the multiple codewords. The decoder determines an inter-set delay for a codeword of a select memory set. When the inter-set delay is greater than a maximum inter-set delay, the decoder determines a total decoding time based on an effective inter-set delay and an effective decoding time. The decoder outputs the decoded codeword at the end of the total decoding time.

Abstract: Devices, systems and methods for reducing complexity of a bit-flipping decoder for quasi-cyclic (QC) low-density parity-check (LDPC) codes are described. An example method includes receiving a noisy codeword that is based on a transmitted codeword generated from an irregular QC-LDPC code, the irregular QC-LDPC code having an associated parity matrix, storing, based on a weight of a plurality of columns of the parity matrix of the irregular QC-LDPC code, a portion of the noisy codeword corresponding to the plurality of columns in a first buffer of a plurality of buffers, and accessing and processing the portion of the noisy codeword that includes applying a vertically shuffled scheduling (VSS) scheme that uses a plurality of processing units to determine a candidate version of a portion of the transmitted codeword that corresponds to the portion of the noisy codeword.

Abstract: Disclosed are devices, systems and methods improving the convergence of a soft bit-flipping decoder in a non-volatile memory device. An example method includes receiving a noisy codeword, the codeword having been generated based on a parity check matrix of an LDPC code and provided to a communication channel prior to reception by the soft bit-flipping decoder, generating, based on the noisy codeword, one or more messages for passing between a plurality of variable nodes and a plurality of check nodes of the soft bit-flipping decoder, generating a reliability metric for each of the one or more messages, storing the reliability metric only for messages comprising magnitudes that are less than or equal to a predetermined threshold value; and performing, based on the one or more messages and the associated reliability metric for at least one of the one more messages, a single decoding iteration of the soft bit-flipping decoder.

Abstract: Disclosed are devices, systems and methods for improving a bit-flipping algorithm for an irregular LDPC code in a non-volatile memory device. An example method includes receiving a noisy codeword, the codeword having been generated from an irregular low-density parity-check code, performing a first iteration of a bit-flipping algorithm on the noisy codeword, computing a first syndrome based on an output codeword of the first iteration, determining that the first syndrome comprises a non-zero vector and no bits of the noisy codeword were flipped during the first iteration of the bit-flipping algorithm, flipping, based on the determining, at least one bit of the output codeword, the at least one bit corresponding to a variable node of the plurality of variable nodes with a smallest column weight connected to one or more unsatisfied check nodes of the plurality of check nodes, and computing, subsequent to the flipping, a second syndrome.