Abstract: Disclosed are devices, systems and methods improving the convergence of a bit-flipping decoder in a non-volatile memory device. An example method includes receiving a noisy codeword, the codeword having been generated based on a parity check matrix of a low-density parity-check code and provided to a communication channel prior to reception by the bit-flipping decoder, and performing a single decoding iteration on the received noisy codeword, the single decoding iteration spanning a plurality of stages. In some embodiments, performing a single decoding iteration includes computing a metric corresponding to a single column of the parity check matrix, flipping at least one bit in the single column upon a determination that the metric exceeds a flipping threshold, computing, subsequent to the flipping, a syndrome as a product of the noisy codeword and the parity check matrix, and updating the flipping threshold upon a determination that the syndrome is not zero.

Abstract: Disclosed are devices, systems and methods improving the convergence of a bit-flipping decoder in a non-volatile memory device. An example method includes receiving a noisy codeword, the codeword having been generated based on a parity check matrix of a low-density parity-check code and provided to a communication channel prior to reception by the bit-flipping decoder, and performing a single decoding iteration on the received noisy codeword, the single decoding iteration spanning a plurality of stages. In some embodiments, performing a single decoding iteration includes computing a metric corresponding to a single column of the parity check matrix, flipping at least one bit in the single column upon a determination that the metric exceeds a flipping threshold, computing, subsequent to the flipping, a syndrome as a product of the noisy codeword and the parity check matrix, and updating the flipping threshold upon a determination that the syndrome is not zero.

Abstract: Disclosed are devices, systems and methods improving the convergence of a soft bit-flipping decoder in a non-volatile memory device. An example method includes receiving a noisy codeword, the codeword having been generated based on a parity check matrix of an LDPC code and provided to a communication channel prior to reception by the soft bit-flipping decoder, generating, based on the noisy codeword, one or more messages for passing between a plurality of variable nodes and a plurality of check nodes of the soft bit-flipping decoder, generating a reliability metric for each of the one or more messages, storing the reliability metric only for messages comprising magnitudes that are less than or equal to a predetermined threshold value; and performing, based on the one or more messages and the associated reliability metric for at least one of the one more messages, a single decoding iteration of the soft bit-flipping decoder.

Abstract: An encoder for use in a memory system receives data bits and position information regarding a storage area among storage areas of a memory device in which the data bits are to be stored, determining the number of multiple random sequences to be used based on the position information, scrambling the data bits using the determined number of multiple random sequences, to generate scrambled sequences, selecting from among the generated scrambled sequences the scrambled sequence having the lowest number of a particular logic value, and outputting the selected scrambled sequence for storage in the storage area of the memory device.

Abstract: Memory controllers bit-flipping (BF) decoders and methods that selectively apply a checksum-aided error reduction (CA-ER) scheme to BF decoding of a low-density parity-check (LDPC) code. In decoding a codeword, a hard decision value resulting from decoding a select variable node is changed when a first condition is satisfied to yield an updated hard decision value. Also, when the first condition is satisfied, a current checksum value after processing the select variable node is updated using the updated hard decision value. The CA-ER scheme is applied when the updated checksum value is not reduced to a set minimum and a second condition based on a previous checksum value, calculated after a previous variable node is processed, is satisfied.

Abstract: Embodiments describe a method for reading data from storage that includes selecting a block of memory to read, identifying a read retry table for reading the block, determining that the read retry table for the selected block of memory needs to be updated, and reading the block of memory using a new set of read threshold voltages from the read retry table. Responsive to a successful read operation using the new set of voltages, the method can also include replacing the initial set of read voltages in the first field with the new set of read voltages, and filling the plurality of subsequent fields in the read retry table with additional sets of read threshold voltages identified from a read retry neighbor table, where at least one of the additional sets of read voltages is closest in distance to the initial set of read voltages in read voltage space.

Abstract: An encoder for use in a memory system receives data bits and position information regarding a storage area among storage areas of a memory device in which the data bits are to be stored, determining the number of multiple random sequences to be used based on the position information, scrambling the data bits using the determined number of multiple random sequences, to generate scrambled sequences, selecting from among the generated scrambled sequences the scrambled sequence having the lowest number of a particular logic value, and outputting the selected scrambled sequence for storage in the storage area of the memory device.

Abstract: Memory controllers, decoders and methods to selectively perform bit-flipping (BF) decoding and min-sum (MS) decoding on codewords of an irregular low-density parity-check (LDPC) code. Bit-flipping (BF) decoding is executed with respect to variable nodes having relatively high column weights. MS decoding is executed with respect to variable nodes having relatively low column weights. A column-weight threshold is used to group the variable nodes into the higher and lower column weight groups. The two decoding techniques exchange results during the overall decoding process.

Abstract: A high throughput communication apparatus which provides low frame error rates (FER). Error checking encoder and decoders which each comprise a plurality of short blocklength error checking encoders or decoders, respectively, in parallel, coupled through common incremental redundancy. Short-blocklength codes are utilized to achieve communication capacity with incremental redundancy. The system can transmit and decode a large number of short-blocklength codewords in parallel, while it delivers incremental redundancy, without feedback, only to the decoders that need incremental redundancy.

Abstract: A high throughput communication apparatus which provides low frame error rates (FER). Error checking encoder and decoders which each comprise a plurality of short blocklength error checking encoders or decoders, respectively, in parallel, coupled through common incremental redundancy. Short-blocklength codes are utilized to achieve communication capacity with incremental redundancy. The system can transmit and decode a large number of short-blocklength codewords in parallel, while it delivers incremental redundancy, without feedback, only to the decoders that need incremental redundancy.

Abstract: The present invention provides an encryption and decryption method and device. In the method, a first optical transport network (OTN) transport device encrypts, according to an initial vector (IV), a key, and an encryption algorithm that are preset, data received by the first OTN transport device, and sends the IV and the encrypted data to a second OTN transport device; and the second OTN transport device receives a value of a high-order counter in the IV and the encrypted data that are sent by the first OTN transport device, where the encrypted data is data encrypted by using the IV, the preset key, and the encryption algorithm, and decrypts the encrypted data according to the preset key, the IV, and a decryption algorithm corresponding to the encryption algorithm.

Abstract: The present invention provides an encryption and decryption method and device. In the method, a first optical transport network (OTN) transport device encrypts, according to an initial vector (IV), a key, and an encryption algorithm that are preset, data received by the first OTN transport device, and sends the IV and the encrypted data to a second OTN transport device; and the second OTN transport device receives a value of a high-order counter in the IV and the encrypted data that are sent by the first OTN transport device, where the encrypted data is data encrypted by using the IV, the preset key, and the encryption algorithm, and decrypts the encrypted data according to the preset key, the IV, and a decryption algorithm corresponding to the encryption algorithm.

Abstract: A call signaling protocol that uses simplified messaging to set up, confirm set up, tear down, and confirm tear down of a connection. The available capacity of communications links is tracked so that it can be quickly determined whether or not a link can handle a call. Segments (e.g., time slots, wavelengths, etc.) of a link having enough available capacity are allocated by a separate operation. Connection state information is also tracked. The simple messages and information used by the signaling protocol permits it to be easily implemented in hardware. Such an implementation enables high-speed, high-capacity, call signaling.

Abstract: A call signaling protocol that uses simplified messaging to set up, confirm set up, tear down, and confirm tear down of a connection. The available capacity of communications links is tracked so that it can be quickly determined whether or not a link can handle a call. Segments (e.g., time slots, wavelengths, etc.) of a link having enough available capacity are allocated by a separate operation. Connection state information is also tracked. The simple messages and information used by the signaling protocol permits it to be easily implemented in hardware. Such an implementation enables high-speed, high-capacity, call signaling.