Abstract: The present application provides a display substrate, a display panel and a spliced screen, and belongs to the field of display technology. The display substrate in the present application is divided into display and boding regions, and includes a base substrate, and a pixel driving circuit on the base substrate and corresponding to the display region. The display substrate further includes an interlayer insulating layer and a signal lead-in wire on the base substrate. The signal lead-in wire at least includes a first signal lead-in sub-wire on a side of the interlayer insulating layer away from the base substrate. The first signal lead-in sub-wire is connected to a first connection pad in the bonding region for introducing an external signal to the pixel driving circuit. The interlayer insulating layer includes sub-insulating layers defining a multi-stepped structure at a position where the display region is adjacent to the bonding region.

Abstract: A pixel circuit, a driving method thereof and a light emitting device, and relates to the technical field of display. The pixel circuit comprises driving sub-circuit comprising a control terminal, first terminal and a second terminal, driving sub-circuit being configured to control driving signal flowing through the first terminal and second terminal according to signal of control terminal; first capacitor comprising first pole and second pole coupled to control terminal of driving sub-circuit; first data writing sub-circuit configured to write first initialization signal to first pole of first capacitor in response to first scanning signal, write first data signal into driving sub-circuit in response to first scanning signal, so that signal of control signal of driving sub-circuit changes with first data signal; second data writing sub-circuit configured to write second data signal to first pole of first capacitor in response to second scanning signal.

Abstract: The present disclosure provides a pixel driving structure and a display panel. The pixel driving structure includes a pulse width modulation driving circuit, a pulse amplitude modulation driving circuit, and a buffer circuit. The pulse width modulation driving circuit is configured to control a pulse width of a driving current supplied to the light emitting device to be driven according to a pulse width modulation data voltage; the pulse amplitude modulation driving circuit is configured to control an amplitude of the driving current supplied to the light emitting device to be driven according to a pulse amplitude modulation data voltage; and the buffer circuit is electrically coupled between the pulse width modulation driving circuit and the pulse amplitude modulation driving circuit and is configured to adjust a rate at which the pulse width modulation driving circuit applies a pulse width modulation voltage to the pulse amplitude modulation driving circuit.

Abstract: An array substrate, a detection method for the array substrate, and a tiled display panel. In the array substrate, each of pixels (1) comprises sub-pixels (01) of at least three colors and a. pixel driving chip (02) for driving each sub-pixel (01) to emit light; each sub-pixel (01) comprises at least one inorganic light-emitting diode; a display area (A1) further comprises: a positive signal line (Tian) connected to a positive electrode of each inorganic light-emitting diode, and a data signal line (Din), a scanning line (Sn), and a reference signal line (Vm) connected to each pixel driving chip (02); each pixel driving chip (02) is used for writing signals of the data signal line (Dm) into the sub-pixels (01) of different colors under the control of the corresponding scanning line (Sn) in a time division manner.

Abstract: A shift register includes: an input circuit for transmitting an input signal to a first node under control of a first clock signal, and for transmitting the first clock signal to the second node under control of a level of the first node; a control circuit for transmitting a second power supply signal to the first node under control of a level of the second node and a second clock signal, for transmitting the second clock signal to the third node under control of a level of the fourth node and/or the first; a pull-down control circuit; and an output circuit for transmitting the fourth power supply signal or the third power supply signal to the signal output terminal. The pull-down control circuit controls a level of the fifth node regardless of the first clock signal.

Abstract: A shift register, a driving method, a driving control circuit and a display device. The method comprises: at a data refresh stage (T10), applying to an input signal end (IP) an input signal having a pulse level, applying a control clock pulse signal to a control clock signal end, and applying a noise reduction clock pulse signal to a noise reduction clock signal end; at a noise reduction holding phase (T21-1), applying a fixed voltage signal to the input signal end (IP), applying a fixed voltage signal to the control clock signal end, and applying a fixed voltage signal to the noise reduction clock signal end; and at a noise reduction enhancement stage (T22-1), applying a fixed voltage signal to the input signal end (IP), applying a fixed voltage signal to the control clock signal end, and applying a clock pulse signal to the noise reduction clock signal end.

Abstract: A pixel drive circuit includes a data write sub-circuit, an input and read sub-circuit, a drive sub-circuit, and a first output control sub-circuit. The data write sub-circuit is configured to transmit data signals input from a first data voltage terminal at different times to a first node. The input and read sub-circuit is configured to: transmit a signal of a signal transmission terminal to a second node in a write period, and transmit an electrical signal of the second node to the signal transmission terminal in a threshold voltage read period. The drive sub-circuit is configured to output a drive signal. The first output control sub-circuit is configured to: be coupled to an element to be driven, and transmit the drive signal output by the drive sub-circuit to the element to be driven.

Abstract: An alignment mark includes a first alignment marker located on a first surface of a substrate and a second alignment marker located on a second surface of the substrate. The second alignment marker is arranged to be matched with the first alignment marker, and capable of representing a process variation between the second alignment marker and the first alignment marker.

Abstract: The present application provides a pixel circuit, a pixel driving method and a display device. The pixel circuit is to be coupled to a to-be-driven element. The pixel circuit includes a first energy storage circuit, a driving circuit, a light-emitting control circuit, a data writing circuit, and a compensation control circuit. The compensation control circuit is configured to, under control of a third control signal, control conduction between the first node and the first terminal of the driving circuit, and control conduction between the second node and the second terminal of the driving circuit.

Abstract: A pixel circuit includes a driving circuit, a first control circuit and a second control circuit. The driving circuit is configured to receive a data signal in response to a scan signal, and generate, in response to a first enable signal, a driving signal according to a first voltage and the data signal. The first control circuit is configured to: receive a first input signal in response to a first control signal, and transmit a third input signal in response to the first input signal; and receive a second input signal in response to a second control signal, and transmit a second enable signal in response to the second input signal. The second control circuit is configured to transmit the driving signal to an element to be driven in response to one of the third input signal and the second enable signal.

Abstract: A shift register (SR) includes a voltage control circuit (110) and a bias compensation circuit (120). The voltage control circuit (110) is configured to control a voltage at a first node (Output) to be a first voltage or a second voltage. The bias compensation circuit (120) is configured to: when the voltage at the first node (Output) is the first voltage, transmit a first signal received by a first signal terminal (VDD-A) to a first signal output terminal (EM1), and transmit a second signal received by a second signal terminal (VDD-B) to a second signal output terminal (EM2); and in response to the voltage at the first node (Output) being the second voltage, transmit a signal received by a first voltage terminal (LVGL1) to the first signal output terminal (EM1) and the second signal output terminal (EM2).

Abstract: The present disclosure provides a pixel driving circuit and a display panel. The pixel driving circuit includes: a data writing sub-circuit configured to transmit a data voltage signal to a first terminal of a driving sub-circuit in response to a first scanning signal; a threshold compensation sub-circuit configured to compensate for a threshold voltage of the driving sub-circuit in response to a second scanning signal; a storage sub-circuit configured to store the data voltage signal; the driving sub-circuit configured to provide a driving current for a light emitting device to be driven according to voltages of a first terminal and a control terminal of the driving sub-circuit; and a voltage maintaining sub-circuit configured to maintain the voltage of the control terminal of the driving sub-circuit when the voltage of the first terminal of the driving sub-circuit jumps.

Abstract: A pixel circuit includes a current control sub-circuit, a combined light emitting sub-circuit, and a first light emitting element to an Nth light emitting element, N being a natural number greater than 1. The current control sub-circuit is configured to receive a display data signal and a light emitting control signal, control whether to generate a driving current according to the light emitting control signal, and control a current intensity of the generated driving current according to the display data signal. The combined light emitting sub-circuit is configured to receive the driving current and a first light emitting data signal to an Nth light emitting data signal and drive one or more of the first light emitting element to the Nth light emitting element to emit light according to the first light emitting data signal to the Nth light emitting data signal.

Abstract: A pixel driving circuit includes a data writing sub-circuit, a driving sub-circuit, and a control sub-circuit. The data writing sub-circuit is configured to: in response to a first scanning signal and a third scanning signal, write a first data signal into the driving sub-circuit; and in response to a second scanning signal and the third scanning signal, write a second data signal into the driving sub-circuit. The control sub-circuit is configured to, in response to an enable signal, connect a driving transistor to a first power supply voltage signal terminal and an element to be driven. The driving sub-circuit is configured to: according to the first data signal and a first power supply voltage signal, output a driving to signal; and according to the second data signal and the first power supply voltage signal, control an operating state of the element to be driven.

Abstract: A drive back plate is provided. The drive back plate includes a base substrate, and a drive circuit and a bonding structure disposed on the base substrate. The drive circuit includes a target drive structure, and a film layer disposed on at least one side of the target drive structure and adjacent to the target drive structure in the drive back plate is an inorganic insulating layer. The bonding structure is disposed on the same layer as the target drive structure, and the material of the bonding structure is the same as the material of the target drive structure.

Abstract: A driving backplane, a display panel and a display device are disclosed. The driving backplane includes: a base substrate; a plurality of pixel driving circuits located on the base substrate; an electrode located on a side of each of the pixel driving circuits facing away from the base substrate and coupled with the pixel driving circuits; and a potential wire located between the electrode and the base substrate and coupled with the pixel driving circuits. Every at least two pixel driving circuits are coupled with a same signal line through a multiplexing controller, an orthographic projection of the controller on the base substrate completely falls into a range of a corresponding micro light emitting diode bonding region, and an orthographic projection of a control wire coupled with the controller on the base substrate completely falls into a range of an orthographic projection of the potential wire on the base substrate.

Abstract: The present application provides a pixel circuit, a pixel driving method and a display device. The pixel circuit is to be coupled to a to-be-driven element. The pixel circuit includes a first energy storage circuit, a driving circuit, a light-emitting control circuit, a data writing circuit, and a compensation control circuit. The compensation control circuit is configured to, under control of a third control signal, control conduction between the first node and the first terminal of the driving circuit, and control conduction between the second node and the second terminal of the driving circuit.

Abstract: Disclosed is an array substrate including multiple first selection circuits with each including at least two first selection transistors and at least two first anticreeping transistors. Each first selection transistor is connected with one first anticreeping transistor in series. When the first selection transistor is turned on by a first turn-on signal from a first control signal terminal, the first anticreeping transistor is turned on by a second turn-on signal from a second control signal terminal. When the first selection transistor is turned off by a first turn-off signal from the first control signal terminal, the first anticreeping transistor is turned off to make the first selection transistors and the data signal terminal disconnected, by a second turn-off signal from the second control signal terminal. A voltage of the first turn-off signal is greater than a voltage of the second turn-off signal.

Abstract: An array substrate includes pixel group(s) and pixel circuit group(s), each pixel group includes pixels, and each pixel includes sub-pixel(s). At least two pixel groups are arranged in a row direction; in a column direction, a length of a pixel group is greater than a length of a pixel circuit group electrically connected thereto; and orthographic projections of a sub-pixel and a pixel circuit group electrically connected to a pixel group to which the sub-pixel belongs on a plane does not overlap. Or, the at least two pixel groups are arranged in the column direction; in the row direction, a length of a pixel group is greater than a length of a pixel circuit group electrically connected thereto; and orthographic projections of a sub-pixel and a pixel circuit group electrically connected to a pixel group to which the sub-pixel belongs on another plane does not overlap.

Abstract: A pixel circuit includes an input circuit and a time control circuit. The input circuit includes a driving transistor, and the input circuit is configured to write a data signal into a gate of the driving transistor in response to a first gate signal, so that the driving transistor outputs a driving signal for driving an element to be driven to emit light according to a gate voltage and a source voltage thereof. The time control circuit is coupled to the input circuit and the element to be driven, and is configured to control the input circuit to transmit the driving signal to the element to be driven for a first duration, and control the input circuit to transmit the driving signal to the element to be driven for a second duration. The second duration is shorter than the first duration, and includes a plurality of phases spaced apart.