Abstract: Photovoltaic devices and methods for preparing a p-type semiconductor layer for the photovoltaic devices generally include electroplating a layer of gallium or a gallium alloy onto a conductive layer by contacting the conductive layer with a plating bath free of complexing agents including a gallium salt, methane sulfonic acid or sodium sulfate and an organic additive comprising at least one nitrogen atom and/or at least one sulfur atom, and a solvent; adjusting a pH of the solution to be less than 2.6 or greater than 12.6. The photovoltaic device includes an impurity in the p-type semiconductor layer selected from the group consisting of arsenic, antimony, bismuth, and mixtures thereof. Various photovoltaic precursor layers for forming CIS, CGS and CIGS p-type semiconductor structures can be formed by electroplating the gallium or gallium alloys in this manner. Also disclosed are processes for forming a thermal interface of gallium or a gallium alloy with the electroplating process.

Abstract: Solutions and processes for electrodepositing gallium or gallium alloys includes a plating bath free of complexing agents including a gallium salt, an indium salt, a combination thereof, and a combination of any of the preceding salts with copper, an acid, and a solvent, wherein the pH of the solution is in a range selected from the group consisting of from about zero to about 2.6 and greater than about 12.6 to about 14. An optional metalloid may be included in the solution.

Abstract: A structure and method of making a thin-film solar cell. A thin-film solar cell includes a substrate, absorber layer and a buffer layer. The absorber layer is deposited by a single-step bulk electrochemical process, or a multi-layer electrochemical process. The buffer layer is deposited by an electrochemical deposition process such as a multi-layer deposition or an atomic layer deposition. The absorber and buffer layers are non-toxic materials which can include sulfur incorporated during the deposition process or incorporated after deposition by an anneal step.

Abstract: An electroplating apparatus is provided that includes a plating tank for containing a plating electrolyte. A counter electrode, e.g., anode, is present in a first portion of the plating tank. A cathode system is present in a second portion of the plating tank. The cathode system includes a working electrode and a thief electrode. The thief electrode is present between the working electrode and the counter electrode. The thief electrode includes an exterior face that is in contact with the plating electrolyte that is offset from the plating surface of the working electrode. In one embodiment, the thief electrode overlaps a portion of the working electrode about the perimeter of the working electrode. In one embodiment, a method is provided of using the aforementioned electroplating apparatus that provides increased uniformity in the plating thickness.

Abstract: An integrated photovoltaic cell and battery device, a method of manufacturing the same and a photovoltaic power system incorporating the integrated photovoltaic cell and battery device. The integrated photovoltaic cell and battery device includes a photovoltaic cell, a battery, and interconnects providing three-dimensional integration of the photovoltaic cell and the battery into an integrated device for capturing and storing solar energy. Also provided is a design structure readable by a machine to simulate, design, or manufacture the above integrated photovoltaic cell and battery device.

Abstract: An electroplating apparatus including a reference electrode to control the potential during an electro-deposition process. The electroplating apparatus may include a bath containing a plating electrolyte and an anode present in a first portion of the bath containing the plating electrolyte. A cathode is present in a second portion of the bath containing the plating electrolyte. A reference electrode is present at a perimeter of the cathode. The electroplating apparatus also includes a control system to bias the cathode and the anode to provide a potential. A measuring system is provided in electrical communication with the reference electrode to measure the potential of the cathode. Methods of using the above described electroplating apparatus are also provided. Structures and method for electroless deposition are also provided.

Abstract: An electroplating/etch apparatus including a fluid jet and a dryer present over the tank containing the electrolyte for the electroplating/etch process. The fluid jet and the dryer remove excess liquids, such as electrolyte, from the component being plated or etched, e.g., working electrode. The working electrode is present on a holder that traverses from a first position within the tank during a plating or etch operation to a second position that is outside the containing the plating electrolyte. The fluid jet rinses the working electrode when the holder is in the second position, and the forced air dryer blows any remaining fluid from the fluid jet and the electrolyte from the working electrode into the tank.

Abstract: A nanostructure comprising germanium, including wires of less than 1 micron in diameter and walls of less than 1 micron in width, in contact with the substrate and extending outward from the substrate is provided along with a method of preparation.

Abstract: A contact metallurgy structure comprising a patterned dielectric layer having vias on a substrate; a silicide layer of cobalt and/or nickel located at the bottom of vias; a contact layer comprising Ti located in vias on top of the silicide layer; a diffusion layer located in vias and on top of the contact layer; a metal fill layer in vias is provided along with a method of fabrication. The metal fill layer comprises at least one member selected from the group consisting of copper, ruthenium, rhodium platinum, palladium, iridium, rhenium, tungsten, gold, silver and osmium and alloys thereof. When the metal fill layer comprises rhodium, the diffusion layer is not required. Optionally a seed layer for the metal fill layer can be employed.

Abstract: The present invention provides a method of forming an electrode having reduced corrosion and water decomposition on a surface thereof. A conductive layer is deposited on a substrate. The conductive layer is partially oxidized by an oxygen plasma process to convert a portion thereof to an oxide layer thereby forming the electrode. The oxide layer is free of surface defects and the thickness of the oxide layer is from about 0.09 nm to about 10 nm and ranges therebetween, controllable with 0.2 nm precision.

Abstract: The present invention provides a method of reducing corrosion and water decomposition on a surface of an electrode having a titanium nitride conductive layer disposed on a substrate and estimating extent of reduction thereof. The electrode is immersed into a solution containing a hydroxyl-functional compound. Thereafter, a voltage is applied to the titanium nitride conductive layer of the electrode. The extent of oxidation of the titanium nitride conductive layer is correlated with the extent of formation of oxide of titanium nitride and/or the extent of oxidation of the titanium nitride conductive layer is correlated with the increase of surface roughness. The extent of water decomposition is correlated with formation of hydrogen and oxygen bubbles.

Abstract: Accordingly, the present invention provides a method of forming an electrode having reduced corrosion and water decomposition on a surface thereof. A substrate which has a conductive layer disposed thereon is provided and the conductive layer has an oxide layer with an exposed surface. The exposed surface of the oxide layer contacts a solution of an organic surface active compound in an organic solvent to form a protective layer of the organic surface active compound over the oxide layer. The protective layer has a thickness of from about 0.5 nm to about 5 nm and ranges therebetween depending on a chemical structure of the surface active compound.

Abstract: An apparatus and method designed to remove metals from a wafer surface using an electrolytic removal process. The apparatus includes a conductive pad having a plurality of alternating cathodes and anodes provided with a power source. The conductive pad is structured and configured to contact all metal islands on a surface of the wafer. Gaps are provided between pairs of the plurality of alternating cathodes and anodes.

Abstract: Stabilized metal gate electrode for complementary metal-oxide-semiconductor (“CMOS”) applications and methods of making the stabilized metal gate electrodes are disclosed. Specifically, the metal gate electrodes are stabilized by alloying wherein the alloy comprises a metal selected from the group consisting of Re, Ru, Pt, Rh, Ni, Al and combinations thereof and an element selected from the group consisting of W, V, Ti, Ta and combinations thereof.

Abstract: A Vertical Field Effect Transistor (VFET) formed on a substrate, with a conductive bottom electrode formed thereon. A bottom dielectric spacer layer and a gate dielectric layer surrounded by a gate electrode are formed thereabove. Thereabove is an upper spacer layer. A pore extends therethrough between the electrodes. A columnar Vertical Semiconductor Nanowire (VSN) fills the pore and between the top and bottom electrodes. An FET channel is formed in a central region of the VSN between doped source and drain regions at opposite ends of the VSN. The gate dielectric structure, that is formed on an exterior surface of the VSN above the bottom dielectric spacer layer, separates the VSN from the gate electrode.

Abstract: Methods for forming photovoltaic devices, methods for forming semiconductor compounds, photovoltaic device and chemical solutions are presented. For example, a method for forming a photovoltaic device comprising a semiconductor layer includes forming the semiconductor layer by electrodeposition from an electrolyte solution. The electrolyte solution includes copper, indium, gallium, selenous acid (H2SeO3) and water.

Abstract: A contact metallurgy structure comprising a patterned dielectric layer having vias on a substrate; a silicide layer of cobalt and/or nickel located at the bottom of vias; a contact layer comprising Ti located in vias on top of the silicide layer; a diffusion layer located in vias and on top of the contact layer; a metal fill layer in vias is provided along with a method of fabrication. The metal fill layer comprises at least one member selected from the group consisting of copper, ruthenium, rhodium platinum, palladium, iridium, rhenium, tungsten, gold, silver and osmium and alloys thereof. When the metal fill layer comprises rhodium, the diffusion layer is not required. Optionally a seed layer for the metal fill layer can be employed.

Abstract: A method of reducing the loss of elements of a photovoltaic thin film structure during an annealing process, includes depositing a thin film on a substrate, wherein the thin film includes a single chemical element or a chemical compound, coating the thin film with a protective layer to form a coated thin film structure, wherein the protective layer prevents part of the single chemical element or part of the chemical compound from escaping during an annealing process, and annealing the coated thin film structure to form a coated photovoltaic thin film structure, wherein the coated photovoltaic thin film retains the part of the single chemical element or the part of the chemical compound that is prevented from escaping during the annealing by the protective layer.

Abstract: A vertical Field Effect Transistor (FET) comprising a vertical semiconductor nanowire is formed by the following steps. Create a columnar pore in a bottom dielectric layer formed on a bottom electrode. Fill the columnar pore by plating a vertical semiconductor nanowire having a bottom end contacting the bottom electrode. Form a doped source region and a doped drain region in the vertical semiconductor nanowire thereby forming an FET device with a FET channel region between the source region and a drain region, which are formed in distal ends of the vertical semiconductor nanowire. Form a gate dielectric layer around the channel region of the vertical semiconductor nanowire. Then form a gate electrode around the gate dielectric layer. Form a top electrode contacting a top end of the vertical semiconductor nanowire.

Abstract: A vertical Field Effect Transistor (FET) comprising a vertical semiconductor nanowire is formed by the following steps. Create a columnar pore in a bottom dielectric layer formed on a bottom electrode. Fill the columnar pore by plating a vertical semiconductor nanowire having a bottom end contacting the bottom electrode. The semiconductor nanowire forms an FET device with a FET channel region between a source region and a drain region formed in distal ends of the vertical semiconductor nanowire. Form a gate dielectric layer around the channel region of the vertical semiconductor nanowire and then form a gate electrode around the gate dielectric layer. Form a top electrode contacting a top end of the vertical semiconductor nanowire.