Patents by Inventor Hariklia Deligianni

Hariklia Deligianni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for electroplating on SOI and bulk semiconductor wafers
    Patent number: 8926805
    Abstract: An electroplating apparatus and method for depositing a metallic layer on the surface of a wafer is provided wherein said apparatus and method do not require physical attachment of an electrode to the wafer. The surface of the wafer to be plated is positioned to face the anode and a plating fluid is provided between the wafer and the electrodes to create localized metallic plating. The wafer may be positioned to physically separate and lie between the anode and cathode so that one side of the wafer facing the anode contains a catholyte solution and the other side of the wafer facing the cathode contains an anolyte solution. Alternatively, the anode and cathode may exist on the same side of the wafer in the same plating fluid. In one example, the anode and cathode are separated by a semi permeable membrane.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Eduard Cartier, Hariklia Deligianni, Rajarao Jammy, Vamsi K. Paruchuri
  • POWER SOURCE ENCAPSULATION
    Publication number: 20140356699
    Abstract: A system includes a power source having a set of power terminals, a cover encapsulating the power source including the set of power terminals and sealing the power source including the set of power terminals within the cover, and a set of conductive contacts passing through the cover, contacting the set of power terminals, and providing conductive access to the set of power terminals of the power source from outside the cover without allowing exposure of the power source to an environment outside the cover.
    Type: Application
    Filed: May 28, 2013
    Publication date: December 4, 2014
    Inventors: Hariklia Deligianni, Dimitri Kanevsky, Nina Sainath, Tara N. Sainath
  • POWER SOURCE ENCAPSULATION
    Publication number: 20140352139
    Abstract: A method comprising the steps of encapsulating a power source including a set of power terminals in a cover and sealing the power source including the set of power terminals within the cover and inserting a set of conductive contacts through the cover to contact the set of power terminals and provide conductive access to the set of power terminals of the power source from outside the cover without allowing exposure of the power source to an environment outside the cover.
    Type: Application
    Filed: August 12, 2013
    Publication date: December 4, 2014
    Inventors: Hariklia Deligianni, Dimitri Kanevsky, Nina Sainath, Tara N. Sainath
  • Method and Chemistry for Selenium Electrodeposition
    Publication number: 20140346051
    Abstract: Techniques for electrodepositing selenium (Se)-containing films are provided. In one aspect, a method of preparing a Se electroplating solution is provided. The method includes the following steps. The solution is formed from a mixture of selenium oxide; an acid selected from the group consisting of alkane sulfonic acid, alkene sulfonic acid, aryl sulfonic acid, heterocyclic sulfonic acid, aromatic sulfonic acid and perchloric acid; and a solvent. A pH of the solution is then adjusted to from about 2.0 to about 3.0. The pH of the solution can be adjusted to from about 2.0 to about 3.0 by adding a base (e.g., sodium hydroxide) to the solution. A Se electroplating solution, an electroplating method and a method for fabricating a photovoltaic device are also provided.
    Type: Application
    Filed: August 13, 2014
    Publication date: November 27, 2014
    Inventors: Shafaat Ahmed, Hariklia Deligianni
  • Plasma annealing of thin film solar cells
    Patent number: 8871560
    Abstract: Embodiments relate to a method for annealing a solar cell structure including forming an absorber layer on a molybdenum (Mo) layer of a solar cell base structure. The solar cell base structure includes a substrate and the Mo layer is located on the substrate. The absorber layer includes a semiconductor chalcogenide material. Annealing the solar cell base structure is performed by exposing an outer layer of the solar cell base structure to a plasma.
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: October 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Shafaat Ahmed, Sukjay Chey, Hariklia Deligianni, Lubomyr T. Romankiw
  • Method and chemistry for selenium electrodeposition
    Patent number: 8840770
    Abstract: Techniques for electrodepositing selenium (Se)-containing films are provided. In one aspect, a method of preparing a Se electroplating solution is provided. The method includes the following steps. The solution is formed from a mixture of selenium oxide; an acid selected from the group consisting of alkane sulfonic acid, alkene sulfonic acid, aryl sulfonic acid, heterocyclic sulfonic acid, aromatic sulfonic acid and perchloric acid; and a solvent. A pH of the solution is then adjusted to from about 2.0 to about 3.0. The pH of the solution can be adjusted to from about 2.0 to about 3.0 by adding a base (e.g., sodium hydroxide) to the solution. A Se electroplating solution, an electroplating method and a method for fabricating a photovoltaic device are also provided.
    Type: Grant
    Filed: September 9, 2010
    Date of Patent: September 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Shafaat Ahmed, Hariklia Deligianni
  • Structure and Method of Fabricating a CZTS Photovoltaic Device by Electrodeposition
    Publication number: 20140252530
    Abstract: Techniques for using electrodeposition to form absorber layers in diodes (e.g., solar cells) are provided. In one aspect, a method for fabricating a diode is provided. The method includes the following steps. A substrate is provided. A backside electrode is formed on the substrate. One or more layers are electrodeposited on the backside electrode, wherein at least one of the layers comprises copper, at least one of the layers comprises zinc and at least one of the layers comprises tin. The layers are annealed in an environment containing a sulfur source to form a p-type CZTS absorber layer on the backside electrode. An n-type semiconductor layer is formed on the CZTS absorber layer. A transparent conductive layer is formed on the n-type semiconductor layer. A diode is also provided.
    Type: Application
    Filed: May 23, 2014
    Publication date: September 11, 2014
    Applicant: International Business Machines Corporation
    Inventors: Shafaat Ahmed, Hariklia Deligianni, Lubomyr T. Romankiw, Kejia Wang
  • Solar cell and battery 3D integration
    Patent number: 8829329
    Abstract: An integrated photovoltaic cell and battery device, a method of manufacturing the same and a photovoltaic power system incorporating the integrated photovoltaic cell and battery device. The integrated photovoltaic cell and battery device includes a photovoltaic cell, a battery, and interconnects providing three-dimensional integration of the photovoltaic cell and the battery into an integrated device for capturing and storing solar energy. Also provided is a design structure readable by a machine to simulate, design, or manufacture the above integrated photovoltaic cell and battery device.
    Type: Grant
    Filed: August 18, 2010
    Date of Patent: September 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Hariklia Deligianni, Fei Liu
  • Electrodeposition method for forming Ge on semiconductor substrates
    Patent number: 8823143
    Abstract: Methods for electrodepositing germanium on various semiconductor substrates such as Si, Ge, SiGe, and GaAs are provided. The electrodeposited germanium can be formed as a blanket or patterned film, and may be crystallized by solid phase epitaxy to the orientation of the underlying semiconductor substrate by subsequent annealing. These plated germanium layers may be used as the channel regions of high-mobility channel field effect transistors (FETs) in complementary metal oxide semiconductor (CMOS) circuits.
    Type: Grant
    Filed: August 14, 2009
    Date of Patent: September 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Hariklia Deligianni, Qiang Huang, Lubomyr T. Romankiw, Devendra K. Sadana, Katherine L. Saenger
  • Battery with self-programming fuse
    Patent number: 8790804
    Abstract: A useful lifetime of an energy storage device can be extended by providing a series connection of a battery cell and an self-programming fuse. A plurality of series connections of a battery cell and an self-programming fuse can then be connected in a parallel connection to expand the energy storage capacity of the energy storage device. Each self-programming fuse can be a strip of a metal semiconductor alloy material, which electromigrates when a battery cell is electrically shorted and causes increases in the amount of electrical current therethrough. Thus, each self-programming fuse is a self-programming circuit that opens once the battery cell within the same series connection is shorted.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: July 29, 2014
    Assignee: International Business Machines Corporation
    Inventors: Hariklia Deligianni, Harold J. Hovel, Fei Liu
  • Structure and method of fabricating a CZTS photovoltaic device by electrodeposition
    Patent number: 8790956
    Abstract: Techniques for using electrodeposition to form absorber layers in diodes (e.g., solar cells) are provided. In one aspect, a method for fabricating a diode is provided. The method includes the following steps. A substrate is provided. A backside electrode is formed on the substrate. One or more layers are electrodeposited on the backside electrode, wherein at least one of the layers comprises copper, at least one of the layers comprises zinc and at least one of the layers comprises tin. The layers are annealed in an environment containing a sulfur source to form a p-type CZTS absorber layer on the backside electrode. An n-type semiconductor layer is formed on the CZTS absorber layer. A transparent conductive layer is formed on the n-type semiconductor layer. A diode is also provided.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: July 29, 2014
    Assignee: International Business Machines Corporation
    Inventors: Shafaat Ahmed, Hariklia Deligianni, Lubomyr T. Romankiw, Kejia Wang
  • Working electrode design for electrochemical processing of electronic components
    Patent number: 8784618
    Abstract: An electroplating apparatus is provided that includes a plating tank for containing a plating electrolyte. A counter electrode, e.g., anode, is present in a first portion of the plating tank. A cathode system is present in a second portion of the plating tank. The cathode system includes a working electrode and a thief electrode. The thief electrode is present between the working electrode and the counter electrode. The thief electrode includes an exterior face that is in contact with the plating electrolyte that is offset from the plating surface of the working electrode. In one embodiment, the thief electrode overlaps a portion of the working electrode about the perimeter of the working electrode. In one embodiment, a method is provided of using the aforementioned electroplating apparatus that provides increased uniformity in the plating thickness.
    Type: Grant
    Filed: August 19, 2010
    Date of Patent: July 22, 2014
    Assignee: International Business Machines Corporation
    Inventors: Charles L. Arvin, Raschid J. Bezama, Glen N. Biggs, Hariklia Deligianni, Tracy A. Tong
  • Design of 60x120 cm2 Prototype Electrodeposition Cell for Processing of Thin Film Solar Panels
    Publication number: 20140097091
    Abstract: Techniques for electrodeposition of thin film solar panels are provided. In one aspect, an electrodeposition apparatus is provided. The electrodeposition apparatus includes at least one electroplating cell; and a conveyor for moving panels over the electroplating cell, wherein the conveyor comprises at least one metal belted track over the electroplating cell surrounding a plurality of metal rollers. The electroplating cell can include an anode at a bottom of the electroplating cell; and a plurality of paddles at a top of the electroplating cell. A baffle may be located in between the anode and the paddles. An electroplating process is also provided.
    Type: Application
    Filed: October 4, 2012
    Publication date: April 10, 2014
    Applicant: International Business Machines Corporation
    Inventors: Hariklia Deligianni, Lubomyr T. Romankiw
  • PLASMA ANNEALING OF THIN FILM SOLAR CELLS
    Publication number: 20140045295
    Abstract: Embodiments relate to a method for annealing a solar cell structure including forming an absorber layer on a molybdenum (Mo) layer of a solar cell base structure. The solar cell base structure includes a substrate and the Mo layer is located on the substrate. The absorber layer includes a semiconductor chalcogenide material. Annealing the solar cell base structure is performed by exposing an outer layer of the solar cell base structure to a plasma.
    Type: Application
    Filed: August 9, 2012
    Publication date: February 13, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shafaat Ahmed, Sukjay Chey, Hariklia Deligianni, Lubomyr T. Romankiw
  • OHMIC CONTACT OF THIN FILM SOLAR CELL
    Publication number: 20140026949
    Abstract: A chalcogen-resistant material including at least one of a conductive elongated nanostructure layer and a high work function material layer is deposited on a transition metal layer on a substrate. A semiconductor chalcogenide material layer is deposited over the chalcogen-resistant material. The conductive elongated nanostructures, if present, can reduce contact resistance by providing direct electrically conductive paths from the transition metal layer through the chalcogen-resistant material and to the semiconductor chalcogenide material. The high work function material layer, if present, can reduce contact resistance by blocking chalcogenization of the transition metal in the transition metal layer. Reduction of the contact resistance can enhance efficiency of a solar cell including the chalcogenide semiconductor material.
    Type: Application
    Filed: August 10, 2012
    Publication date: January 30, 2014
    Applicant: International Business Machines Corporation
    Inventors: Shafaat AHMED, Hariklia DELIGIANNI, Lubomyr T. ROMANKIW
  • OHMIC CONTACT OF THIN FILM SOLAR CELL
    Publication number: 20140030843
    Abstract: A chalcogen-resistant material including at least one of a carbon nanotube layer and a high work function material layer is deposited on a transition metal layer on a substrate. A semiconductor chalcogenide/kesterite material layer is deposited over the chalcogen-resistant material. The carbon nanotubes, if present, can reduce contact resistance by providing direct electrically conductive paths from the transition metal layer through the chalcogen-resistant material and to the semiconductor chalcogenide material. The high work function material layer, if present, can reduce contact resistance by reducing chalcogenization of the transition metal in the transition metal layer. Reduction of the contact resistance can enhance efficiency of a solar cell including the chalcogenide semiconductor material.
    Type: Application
    Filed: July 26, 2012
    Publication date: January 30, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shafaat Ahmed, Hariklia Deligianni, Lubomyr T. Romankiw
  • Vertical nanowire FET devices
    Patent number: 8637849
    Abstract: A Vertical Field Effect Transistor (VFET) formed on a substrate, with a conductive bottom electrode formed thereon. A bottom dielectric spacer layer and a gate dielectric layer surrounded by a gate electrode are formed thereabove. Thereabove is an upper spacer layer. A pore extends therethrough between the electrodes. A columnar Vertical Semiconductor Nanowire (VSN) fills the pore and between the top and bottom electrodes. An FET channel is formed in a central region of the VSN between doped source and drain regions at opposite ends of the VSN. The gate dielectric structure, that is formed on an exterior surface of the VSN above the bottom dielectric spacer layer, separates the VSN from the gate electrode.
    Type: Grant
    Filed: January 5, 2011
    Date of Patent: January 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Hariklia Deligianni, Qiang Huang, Lubomyr T. Romankiw
  • Forming an electrode having reduced corrosion and water decomposition on surface using a custom oxide layer
    Patent number: 8598018
    Abstract: The present invention provides a method of forming an electrode having reduced corrosion and water decomposition on a surface thereof. A conductive layer is deposited on a substrate. The conductive layer is partially oxidized by an oxygen plasma process to convert a portion thereof to an oxide layer thereby forming the electrode. The oxide layer is free of surface defects and the thickness of the oxide layer is from about 0.09 nm to about 10 nm and ranges therebetween, controllable with 0.2 nm precision.
    Type: Grant
    Filed: June 22, 2010
    Date of Patent: December 3, 2013
    Assignee: International Business Machines Corporation
    Inventors: Ali Afzali-Azdakani, Shafaat Ahmed, Hariklia Deligianni, Dario L. Goldfarb, Stefan Harrer, Hongbo Peng, Stanislav Polonsky, Stephen Rossnagel, Xiaoyan Shao, Gustavo A. Stolovitzky
  • INTERFACE BETWEEN A I-III-VI2 MATERIAL LAYER AND A MOLYBDENUM SUBSTRATE
    Publication number: 20130269780
    Abstract: The present invention relates to a method for fabricating a thin layer made of a alloy and having photovoltaic properties. The method according to the invention comprises first steps of: a) depositing an adaptation layer (MO) on a substrate (SUB), b) depositing at least one layer (SEED) comprising at least elements I and/or III, on said adaptation layer. The adaptation layer is deposited under near vacuum conditions and step b) comprises a first operation of depositing a first layer of I and/or III elements, under same conditions as the deposition of the adaptation layer, without exposing to air the adaptation layer.
    Type: Application
    Filed: December 20, 2011
    Publication date: October 17, 2013
    Applicant: NEXCIS
    Inventors: Pierre-Philippe Grand, Jesus Salvadoe Jaime Ferrer, Emmanuel Roche, Hariklia Deligianni, Raman Vaidyanathan, Kathleen B. Reuter, Qiang Huang, Lubomyr Romankiw, Maurice Mason, Donna S. Zupanski-Nielsen
  • Method and apparatus for electroplating on soi and bulk semiconductor wafers
    Patent number: 8551313
    Abstract: An electroplating apparatus and method for depositing a metallic layer on the surface of a wafer is provided wherein said apparatus and method do not require physical attachment of an electrode to the wafer. The surface of the wafer to be plated is positioned to face the anode and a plating fluid is provided between the wafer and the electrodes to create localized metallic plating. The wafer may be positioned to physically separate and lie between the anode and cathode so that one side of the wafer facing the anode contains a catholyte solution and the other side of the wafer facing the cathode contains an anolyte solution. Alternatively, the anode and cathode may exist on the same side of the wafer in the same plating fluid. In one example, the anode and cathode are separated by a semi permeable membrane.
    Type: Grant
    Filed: November 15, 2007
    Date of Patent: October 8, 2013
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Eduard Cartier, Hariklia Deligianni, Rajarao Jammy, Vamsi K. Paruchuri