Patents by Inventor Harish R

Harish R has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11450392
    Abstract: A processing device in a memory system maintains a counter to track a number of read operations performed on a data block of a memory device and determines that the number of read operations performed on the data block satisfies a first threshold criterion. The processing device further determines whether a number of scan operations performed on the data block satisfies a scan threshold criterion. Responsive to the number of scan operations performed on the data block satisfying the scan threshold criterion, the processing device performs a first data integrity scan to determine one or more first error rates for the data block, each of the one or more first error rates corresponding to a first set of wordlines of the data block, the first set comprising first alternating pairs of adjacent wordlines.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: September 20, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Kishore Kumar Muchherla, Harish R. Singidi, Renato C. Padilla, Vamsi Pavan Rayaprolu, Ashutosh Malshe, Sampath K. Ratnam
  • Patent number: 11443025
    Abstract: A single sign-on system using blockchain is disclosed. The single sign-on system may interconnect various organization systems over a peer-to-peer network, with each organization system having a blockchain node and an application programming interface (API). The blockchain node invokes and uses a smart contract to write registration credentials to the blockchain during a registration process. During a login process, the blockchain node invokes the smart contract to determine whether login credentials match stored login credentials in the blockchain. In response to matching login credentials, the API may generate a single sign-on token that can be used by a user device to access one or more organization systems connected over the network.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: September 13, 2022
    Assignee: AMERICAN EXPRESS TRAVEL RELATED SERVICES COMPANY, INC
    Inventors: Balaji Balaraman, Andras L. Ferenczi, Dallas L. Gale, Nilesh Yashavant Jadhav, Harish R. Naik
  • Patent number: 11436085
    Abstract: Write operations are performed to write data to user blocks of the memory device and to write, to a first set of purposed blocks, purposed data related to the first data written at the memory device. Whether the first set of purposed blocks satisfy a condition indicating an endurance state of the first set of purposed blocks is determined. Responsive to the first set of purposed blocks satisfies the condition, one or more blocks from a pool of storage area blocks of the memory device are allocated to a second set of purposed blocks.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: September 6, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Harish R. Singidi, Ashutosh Malshe, Vamsi Pavan Rayaprolu, Sampath K. Ratnam
  • Publication number: 20220270089
    Abstract: Systems and methods for the maintenance of merchant-stored transaction account data are disclosed. The system may include various merchant systems and issuer systems in communication via a blockchain network. The system provides a process for collaboration between various issuer systems and merchant systems to update and maintain merchant stored transaction account data in response to changes, cancellations, updates, or the like in various stored transaction account.
    Type: Application
    Filed: February 9, 2022
    Publication date: August 25, 2022
    Inventors: FARAZ BABAR, AIMEE CARDWELL, ANDRAS L. FERENCZI, DALLAS GALE, NILESH YASHAVANT JADHAV, ASHISH KUMAR, HARISH R. NAIK, LAVANYA VENKATANARAYANAN
  • Publication number: 20220261313
    Abstract: A parity generation operation based on a set of multiple planes of host data is executed to generate a set of multi-page parity data. The set of multi-page parity data is stored in a cache memory of a memory device. A data recovery operation is performed based on the set of multi-page parity data.
    Type: Application
    Filed: May 2, 2022
    Publication date: August 18, 2022
    Inventors: Xiangang Luo, Jianmin Huang, Lakshmi Kalpana Vakati, Harish R. Singidi
  • Patent number: 11416391
    Abstract: An example apparatus for garbage collection can include a memory including a plurality of mixed mode blocks. The example apparatus can include a controller. The controller can be configured to write a first portion of sequential host data to the plurality of mixed mode blocks of the memory in a single level cell (SLC) mode. The controller can be configured to write a second portion of sequential host data to the plurality of mixed mode blocks in an XLC mode. The controller can be configured to write the second portion of sequential host data by performing a garbage collection operation. The garbage collection operation can include adding more blocks to a free block pool than a quantity of blocks that are written to in association with writing the second portion of sequential host data to the plurality of mixed mode blocks.
    Type: Grant
    Filed: January 14, 2021
    Date of Patent: August 16, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Kishore K. Muchherla, Sampath K. Ratnam, Peter Feeley, Michael G. Miller, Daniel J. Hubbard, Renato C. Padilla, Ashutosh Malshe, Harish R. Singidi
  • Patent number: 11410136
    Abstract: A procurement system and process using blockchain is disclosed. The procurement system may facilitate procurement reconciliation between procurement initiators, clients, suppliers, and/or transaction processors, using blockchain. Each party may comprise a blockchain node configured to interact with a procurement blockchain. The procurement process may be controlled by a billing smart contract and a client smart contract configured to enforce data workflows and establish trust between the parties.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: August 9, 2022
    Assignee: AMERICAN EXPRESS TRAVEL RELATED SERVICES COMPANY, INC.
    Inventors: Jane E. Cook, Andras L. Ferenczi, Nat Grauman, Nilesh Y. Jadhav, Harish R. Naik, Rosa W. Tang
  • Publication number: 20220215389
    Abstract: Systems and methods for transaction authorizations using a distributed database are disclosed. The system may allow registered transaction account holders and merchants to interact and complete transactions according to workflows enforced by smart contracts. The system may include an issuer system that receives a transaction authorization request comprising a merchant ID, a transaction account number, a transaction amount, and a transaction ID. The issuer system may retrieve a merchant public key and a smart contract based on the merchant ID, and a user public key based on the transaction account number. The issuer system may invoke the smart contract by passing the user public key and the transaction ID to the smart contract. The system may propagate transaction data (e.g., the merchant ID, the transaction account number, the payment amount, a transaction status, etc.) to a blockchain network for writing to a blockchain according to the invoked smart contract.
    Type: Application
    Filed: March 24, 2022
    Publication date: July 7, 2022
    Inventors: Balaji Balaraman, Andras L. Ferenczi, Sathish B. Muthukrishnan, Harish R. Naik
  • Patent number: 11379122
    Abstract: A set of memory cells in a data block of a memory component is sampled. A distribution statistic is generated for the data block based on a reliability statistic for each of the set of sampled memory cells. A determination is made based on the distribution statistic of whether the read disturb stress is uniformly or non-uniformly distributed across the data block. In response to a determination that the read disturb stress is non-uniformly distributed across the data block, a first subset of the data block is relocated to another data block of the memory component. The first subset of the data block is associated with a higher concentration of read disturb stress than other subsets of the data block.
    Type: Grant
    Filed: February 18, 2021
    Date of Patent: July 5, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Ashutosh Malshe, Kishore Kumar Muchherla, Vamsi Pavan Rayaprolu, Harish R. Singidi
  • Publication number: 20220179577
    Abstract: A processing device in a memory system receives a first read request from a host system, wherein the first read request is directed to first data stored at a first address in a block of the memory component. The processing device determines that the first address is located within a first region of the block and increments a read counter for the block by a default amount. The processing device further receives a second read request from the host system, wherein the second read request is directed to second data stored at a second address in a block of the memory component, determines that the second address is located within a second region of the block and increments the read counter for the block by a scaled amount.
    Type: Application
    Filed: February 25, 2022
    Publication date: June 9, 2022
    Inventors: Kishore Kumar Muchherla, Ashutosh Malshe, Vamsi Pavan Rayaprolu, Harish R. Singidi, Gianni S. Alsasua
  • Publication number: 20220180922
    Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including performing a first data integrity check on memory pages of a first set of wordlines of the memory device; performing a second data integrity check on memory pages of a second set of wordlines comprising a plurality of wordlines from the first set of wordlines; identifying, among the first set of wordlines and the second set of wordlines, a wordline having a first data state metric value obtained from the first data integrity check equal to a second data state metric value obtained from the second data integrity check; and performing a third data integrity check on a third set of wordlines comprising at least one wordline from the first set of wordlines, wherein the third data integrity check excludes the identified wordline.
    Type: Application
    Filed: February 24, 2022
    Publication date: June 9, 2022
    Inventors: Vamsi Pavan Rayaprolu, Kishore Kumar Muchherla, Harish R. Singidi, Ashutosh Malshe, Gianni S. Alsasua
  • Patent number: 11354037
    Abstract: A system includes a memory component and a processing device to determine an amount of data stored at a region of a memory component and determine, based on the amount of data stored in the region of the memory component. The processing device determines a frequency to perform an operation on one or more memory cells of the region of the memory component. The processing device performs the operation on the one or more memory cells at the frequency to maintain the one or more memory cells of the region of the memory component in a first state associated with a first error rate for data stored at the one or more memory cells. The first error rate is less than a second error rate associated with a second state of the one or more memory cells.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: June 7, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Vamsi Pavan Rayaprolu, Sampath K. Ratnam, Harish R. Singidi, Ashutosh Malshe, Kishore Kumar Muchherla
  • Publication number: 20220139481
    Abstract: A first scan operation of a set of memory pages of a data block is performed using a first reliability threshold level to identify a set of scan results. A workload type associated with the data block is determined based on the set of scan results. The first reliability threshold level is adjusted to a second reliability threshold level based on the workload type. A second scan operation of the set of memory pages of the data block is performed using the second reliability threshold level.
    Type: Application
    Filed: October 30, 2020
    Publication date: May 5, 2022
    Inventors: Vamsi Pavan Rayaprolu, Kishore Kumar Muchherla, Ashutosh Malshe, Gianni S. Alsasua, Harish R. Singidi
  • Patent number: 11321173
    Abstract: Host data to be written to a storage area including a set of multiple planes of a memory device is received. A first parity generation operation based on a portion of the set of multiple planes of the host data to generate a set of multi-plane parity data is executed. The set of multi-plane parity data is stored in in a cache memory of a controller of a memory sub-system. A second parity generation operation based on the set of the multiple planes of the host data to generate a set of multi-page parity data is executed. The set of multi-page parity data in the cache memory of the controller of the memory sub-system is stored. A data recovery operation is performed based on the set of multi-plane parity data and the set of multi-page parity data.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: May 3, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Xiangang Luo, Jianmin Huang, Lakshmi Kalpana K. Vakati, Harish R. Singidi
  • Patent number: 11301146
    Abstract: A memory block of a non-volatile memory device is identified. The memory block has a first region and a second region, where a storage density of the first region is larger than the second region. Data is programmed at the first region of the memory block. An attribute of the memory block based on a sensor is received during programming of the data at the memory block. The attribute characterizes the data being programmed at the first region. The attribute is stored at a volatile during programming of the data at the memory block. The attribute is stored on a memory page of the second region responsive to the programming of the data at the first region being complete.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: April 12, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Vamsi Pavan Rayaprolu, Sampath K. Ratnam, Kishore Kumar Muchherla, Harish R. Singidi, Ashutosh Malshe, Gianni S. Alsasua
  • Patent number: 11287998
    Abstract: A processing device in a memory system receives a first read request from a host system, wherein the first read request is directed to first data stored at a first address in a block of the memory component. The processing device determines that the first address is located within a first region of the block and increments a read counter for the block by a default amount. The processing device further receives a second read request from the host system, wherein the second read request is directed to second data stored at a second address in a block of the memory component, determines that the second address is located within a second region of the block and increments the read counter for the block by a scaled amount.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: March 29, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Kishore Kumar Muchherla, Ashutosh Malshe, Vamsi Pavan Rayaprolu, Harish R. Singidi, Gianni S. Alsasua
  • Patent number: 11282076
    Abstract: Systems and methods for the maintenance of merchant-stored transaction account data are disclosed. The system may include various merchant systems and issuer systems in communication via a blockchain network. The system provides a process for collaboration between various issuer systems and merchant systems to update and maintain merchant-stored transaction account data in response to changes, cancellations, updates, or the like in various stored transaction account.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: March 22, 2022
    Assignee: AMERICAN EXPRESS TRAVEL RELATED SERVICES COMPANY, INC.
    Inventors: Faraz Babar, Aimee Cardwell, Andras L. Ferenczi, Dallas Gale, Nilesh Yashavant Jadhav, Ashish Kumar, Harish R. Naik, Lavanya Venkatanarayanan
  • Patent number: 11282564
    Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including identifying, among a first plurality of wordlines of a set of pages of the memory device, at least one wordline having a current value of a data state metric satisfying a first condition; determining new values of the data state metric of a second plurality of wordlines of the set of pages, wherein the at least one wordline is excluded from the second plurality of wordlines; and responsive to determining that the new values of the data state metric of one or more wordlines of the second plurality of wordlines satisfy a second condition, performing a media management operation with respect to the one or more wordlines.
    Type: Grant
    Filed: November 11, 2020
    Date of Patent: March 22, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Vamsi Pavan Rayaprolu, Kishore Kumar Muchherla, Harish R. Singidi, Ashutosh Malshe, Gianni S. Alsasua
  • Publication number: 20220083408
    Abstract: A method includes obtaining a first operation execution time corresponding to an operation performed on a page of a first data unit of a memory device, determining whether the first operation execution time satisfies a condition that is based on a second operation execution time, wherein the second operation execution time is indicative of lack of defect in at least a second data unit of the memory device, and responsive to determining that the first operation execution time satisfies the condition that is based on the second operation execution time, initiating a defect scan operation of at least a subset of pages of the first data unit.
    Type: Application
    Filed: November 22, 2021
    Publication date: March 17, 2022
    Inventors: Harish R. Singidi, Ashutosh Malshe, Vamsi Pavan Rayaprolu, Kishore Kumar Muchherla
  • Publication number: 20220066678
    Abstract: parity data storage location. Responsive to determining that a first size of the stored parity data satisfies a first condition, the processing device initiates execution of a compression algorithm to compress the stored parity data. Responsive to determining that a second size of the parity data resulting from the execution of the compression algorithm satisfies a second condition, the processing device performs a scan operation to release at least a subset of the stored parity data.
    Type: Application
    Filed: August 25, 2020
    Publication date: March 3, 2022
    Inventors: Harish R. Singidi, Ashutosh Malshe, Vamsi Pavan Rayaprolu, Kishore Kumar Muchherla