Patents by Inventor Harish Reddy Singidi

Harish Reddy Singidi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10930352
    Abstract: Devices and techniques temperature sensitive NAND programming are disclosed herein. A device controller can receive a command to write data to a component of the device. A temperature can be obtained in response to the command, and the temperature can be combined with a temperature compensation value to calculate a verification level. The command can then be executed in accordance with the verification level.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: February 23, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Xiangang Luo, Jianmin Huang, Jung Sheng Hoei, Harish Reddy Singidi, Ting Luo, Ankit Vinod Vashi
  • Patent number: 10915395
    Abstract: Various examples are directed to systems and methods for reading a memory component. A processing device may receive an indication that a read operation at a physical address of the memory component failed. The processing device may execute a plurality of read retry operations at the physical address. The processing device may access a first syndrome weight describing a first error correction operation performed on a result of a first read retry operation of the plurality of read retry operations and a second syndrome weight describing a second error correction operation performed on a result of a second read retry operation of the plurality of read retry operations. The processing device may select a first threshold voltage associated with the first read retry operation based at least in part on the first syndrome weight and the second syndrome weight.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: February 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Ting Luo, Kishore Kumar Muchherla, Harish Reddy Singidi, Xiangang Luo, Renato Padilla, Jr., Gary F. Besinga, Sampath Ratnam, Vamsi Pavan Rayaprolu
  • Publication number: 20210027846
    Abstract: Devices and techniques for initiating and controlling preemptive idle time read scans in a flash based storage system are disclosed. In an example, a memory device includes a NAND memory array and a memory controller to schedule and initiate read scans among multiple locations of the memory array, with such read scans being preemptively triggered during an idle (background) state of the memory device, thus reducing host latency during read and write operations in an active (foreground) state of the memory device. In an example, the optimization technique includes scheduling a read scan operation, monitoring an active or idle state of host IO operations, and preemptively initiating the read scan operation when entering an idle state, before the read scan operation is scheduled to occur. In further examples, the read scan may preemptively occur based on time-based scheduling, frequency-based conditions, or event-driven conditions triggering the read scan.
    Type: Application
    Filed: September 28, 2020
    Publication date: January 28, 2021
    Inventors: Ashutosh Malshe, Harish Reddy Singidi, Kishore Kumar Muchherla, Michael G. Miller, Sampath Ratnam, Xu Zhang, Jie Zhou
  • Publication number: 20210019241
    Abstract: Devices and techniques for a flash memory block retirement policy are disclosed herein. In an example embodiment, a first memory block is provisionally removed from service in response to encountering read errors in the first memory block. Memory pages of the first memory block are tested in a second mode comprising reading memory pages at different read voltages. A raw bit error rate (RBER) or a read window budget (RWB) is determined for memory pages at the different read voltages and the provisionally removed first memory block is returned to service or retired based on the determined RBER or the RWB.
    Type: Application
    Filed: October 7, 2020
    Publication date: January 21, 2021
    Inventors: Harish Reddy Singidi, Giuseppe Cariello, Deping He, Scott Anthony Stoller, Devin Batutis, Preston Allen Thomson
  • Publication number: 20210012851
    Abstract: Disclosed in some examples are NAND devices, firmware, systems, methods, and devices that apply smart algorithms to process ECC errors by taking advantage of excess overprovisioning. In some examples, when the amount of overprovisioned blocks are above a predetermined threshold, a first ECC block error handling mode may be implemented and when the overprovisioned blocks are equal or less than the predetermined threshold, a second mode of ECC block error handling may be utilized.
    Type: Application
    Filed: December 29, 2017
    Publication date: January 14, 2021
    Inventors: Jianmin Huang, Deping He, Xiangang Luo, Harish Reddy Singidi, Kulache Tanpairoj, John Zhang, Ting Luo
  • Patent number: 10892024
    Abstract: A variety of applications can include systems and/or methods of optimizing results from scanning a memory device, where the memory device has stacked multiple reliability specifications. Information about a block of multiple blocks of a memory device can be logged, where the information is associated with a combination of reliability specifications. A refresh of the block can be triggered based on exceeding a threshold condition for the combination of reliability specifications.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: January 12, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Ankit Vashi, Harish Reddy Singidi, Kishore Kumar Muchherla
  • Publication number: 20200411083
    Abstract: Devices and techniques for temperature informed memory refresh are described herein. A temperature counter can be updated in response to a memory device write performed under an extreme temperature. Here, the write is performed on a memory device element in the memory device. The memory device element can be sorted above other memory device elements in the memory device based on the temperature counter. Once sorted to the top of these memory device elements, a refresh can be performed the memory device element.
    Type: Application
    Filed: September 10, 2020
    Publication date: December 31, 2020
    Inventors: Gianni Stephen Alsasua, Harish Reddy Singidi, Kishore Kumar Muchherla, Sampath Ratnam, Ashutosh Malshe, Vamsi Pavan Rayaprolu, Retano Padilla, JR.
  • Publication number: 20200409789
    Abstract: A variety of applications can include apparatus and/or methods that provide parity protection to data spread over multiple memory devices of a memory system. Parity is stored in a buffer, where the parity is generated from portions of data written to a page having a different portion of the page in a portion of each plane of one or more planes of the multiple memory devices. Parity is stored in the buffer for each page. In response to a determination that a transfer criterion is satisfied, the parity data in the buffer is transferred from the buffer to a temporary block. After programming data into the block to close the block, a verification of the block with respect to data errors is conducted. In response to passing the verification, the temporary block can be released for use in a next data write operation. Additional apparatus, systems, and methods are disclosed.
    Type: Application
    Filed: September 10, 2020
    Publication date: December 31, 2020
    Inventors: Harish Reddy Singidi, Xiangang Luo, Preston Allen Thomson, Michael G. McNeeley
  • Publication number: 20200411117
    Abstract: Devices and techniques for read voltage calibration of a flash-based storage system based on host IO operations are disclosed. In an example, a memory device includes a NAND memory array having groups of multiple blocks of memory cells, and a memory controller to optimize voltage calibration for reads of the memory array. In an example, the optimization technique includes monitoring read operations occurring to a respective block, identifying a condition to trigger a read level calibration based on the read operations, and performing the read level calibration for the respective block or a memory component that includes the respective block. In a further example, the calibration is performed based on a threshold voltage to read the respective block, which may be considered when the threshold voltage to read the respective block is evaluated within a sampling operation performed by the read level calibration.
    Type: Application
    Filed: September 10, 2020
    Publication date: December 31, 2020
    Inventors: Ashutosh Malshe, Kishore Kumar Muchherla, Harish Reddy Singidi, Peter Sean Feeley, Sampath Ratnam, Kulachet Tanpairoj, Ting Luo
  • Publication number: 20200371870
    Abstract: A variety of applications can include use of parity groups in a memory system with the parity groups arranged for data protection of the memory system. Each parity group can be structured with multiple data pages in which to write data and a parity page in which to write parity data generated from the data written in the multiple data pages. Each data page of a parity group can have storage capacity to include metadata of data written to the data page. Information can be added to the metadata of a data page with the information identifying an asynchronous power loss status of data pages that precede the data page in an order of writing data to the data pages of the parity group. The information can be used in re-construction of data in the parity group following an uncorrectable error correction code error in writing to the parity group.
    Type: Application
    Filed: August 10, 2020
    Publication date: November 26, 2020
    Inventors: Harish Reddy Singidi, Kishore Kumar Muchherla, Xiangang Luo, Vamsi Pavan Ravaprolu, Ashutosh Malshe
  • Publication number: 20200365219
    Abstract: Disclosed in some examples, are systems, methods, machine-readable mediums, and NAND memory devices which utilize higher read-margin cell types to provide a more granular read disturb indicator without utilizing dummy cells. For example, a NAND architecture may have some cells that are configured as SLC or MLC cells. SLC or MLC cells have more read disturb margin—that is these cells can withstand more read disturb current leakage into the cell before a bit error occurs than TLC or QLC cells. These higher margin cells may serve as the read disturb indicator for a group of cells that have a comparatively lower read disturb margin. Since there are more pages of these higher margin cells than there are pages of dummy cells, these indicators may serve a smaller group of pages than the dummy pages. This reduces the time needed to complete a read disturb scan as fewer pages need to be scanned.
    Type: Application
    Filed: August 6, 2020
    Publication date: November 19, 2020
    Inventors: Harish Reddy Singidi, Scott Anthony Stoller, Jung Sheng Hoei, Ashutosh Malshe, Gianni Stephen Alsasua, Kishore Kumar Muchherla
  • Patent number: 10824527
    Abstract: Devices and techniques for a flash memory block retirement policy are disclosed herein. In an example embodiment, a first memory block is removed from service in response to encountering a read error in the first memory block that exceeds a first error threshold. Recoverable data is copied from the first memory block to a second memory block. During each of multiple iterations, the first memory block is erased and programmed, and each page of the first memory block is read. In response to none of the pages exhibiting a read error that exceeds a second error threshold during the multiple iterations, the first memory block is returned to service.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: November 3, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Harish Reddy Singidi, Giuseppe Cariello, Deping He, Scott Anthony Stoller, Devin Batutis, Preston Allen Thomson
  • Patent number: 10818361
    Abstract: Devices and techniques for initiating and controlling preemptive idle time read scans in a flash based storage system are disclosed. In an example, a memory device includes a NAND memory array and a memory controller to schedule and initiate read scans among multiple locations of the memory array, with such read scans being preemptively triggered during an idle (background) state of the memory device, thus reducing host latency during read and write operations in an active (foreground) state of the memory device. In an example, the optimization technique includes scheduling a read scan operation, monitoring an active or idle state of host IO operations, and preemptively initiating the read scan operation when entering an idle state, before the read scan operation is scheduled to occur. In further examples, the read scan may preemptively occur based on time-based scheduling, frequency-based conditions, or event-driven conditions triggering the read scan.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: October 27, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Ashutosh Malshe, Harish Reddy Singidi, Kishore Kumar Muchherla, Michael G. Miller, Sampath Ratnam, Xu Zhang, Jie Zhou
  • Publication number: 20200335172
    Abstract: Disclosed in some examples, are methods, systems, and machine readable mediums which compensate for read-disturb effects by shifting the read voltages used to read the value in a NAND cell based upon a read counter. For example, the NAND memory device may have a read counter that corresponds to a group of NAND cells (e.g., a page, a block, a superblock). Anytime a NAND cell in the group is read, the read counter may be incremented. The read voltage, Vread, may be adjusted based on the read counter to account for the read disturb voltage.
    Type: Application
    Filed: July 2, 2020
    Publication date: October 22, 2020
    Inventors: Harish Reddy Singidi, Kishore Kumar Muchherla, Gianni Stephen Alsasua, Ashutosh Malshe, Sampath Ratnam, Gary F. Besinga, Micheal G. Miller
  • Publication number: 20200319827
    Abstract: Various examples are directed to systems and methods of managing a memory device. The memory device may receive a read request describing a logical address at the memory device. The memory device may obtain a table entry associated with the logical address. The table entry comprises a physical address corresponding to the logical address and a write temperature data indicating a write temperature for the logical address. The memory device may determine a corrected threshold voltage for reading the physical address based at least in part on the write temperature data and read the physical address using the corrected threshold voltage.
    Type: Application
    Filed: June 23, 2020
    Publication date: October 8, 2020
    Inventors: Gianni Stephen Alsasua, Karl D. Schuh, Ashutosh Malshe, Kishore Kumar Muchherla, Vamsi Pavan Rayaprolu, Sampath Ratnam, Harish Reddy Singidi, Renato Padilla, JR.
  • Patent number: 10796745
    Abstract: Devices and techniques for temperature informed memory refresh are described herein. A temperature counter can be updated in response to a memory device write performed under an extreme temperature. Here, the write is performed on a memory device element in the memory device. The memory device element can be sorted above other memory device elements in the memory device based on the temperature counter. Once sorted to the top of these memory device elements, a refresh can be performed the memory device element.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: October 6, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Gianni Stephen Alsasua, Harish Reddy Singidi, Kishore Kumar Muchherla, Sampath Ratnam, Ashutosh Malshe, Vamsi Pavan Rayaprolu, Renato Padilla, Jr.
  • Patent number: 10789126
    Abstract: A variety of applications can include apparatus and/or methods that provide parity protection to data spread over multiple memory devices of a memory system. Parity is stored in a buffer, where the parity is generated from portions of data written to a page having a different portion of the page in a portion of each plane of one or more planes of the multiple memory devices. Parity is stored in the buffer for each page. In response to a determination that a transfer criterion is satisfied, the parity data in the buffer is transferred from the buffer to a temporary block. After programming data into the block to close the block, a verification of the block with respect to data errors is conducted. In response to passing the verification, the temporary block can be released for use in a next data write operation. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: September 29, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Harish Reddy Singidi, Xiangang Luo, Preston Thomson, Michael G. McNeeley
  • Patent number: 10777284
    Abstract: Devices and techniques for read voltage calibration of a flash-based storage system based on host IO operations are disclosed. In an example, a memory device includes a NAND memory array having groups of multiple blocks of memory cells, and a memory controller to optimize voltage calibration for reads of the memory array. In an example, the optimization technique includes monitoring read operations occurring to a respective block, identifying a condition to trigger a read level calibration based on the read operations, and performing the read level calibration for the respective block or a memory component that includes the respective block. In a further example, the calibration is performed based on a threshold voltage to read the respective block, which may be considered when the threshold voltage to read the respective block is evaluated within a sampling operation performed by the read level calibration.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: September 15, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Ashutosh Malshe, Kishore Kumar Muchherla, Harish Reddy Singidi, Peter Sean Feeley, Sampath Ratnam, Kulachet Tanpairoj, Ting Luo
  • Publication number: 20200278814
    Abstract: Systems and methods are disclosed, comprising a memory device comprising multiple groups of memory cells, the groups comprising a first group of memory cells and a second group of memory cells configured to store information at a same bit capacity per memory cell, and a processing device operably coupled to the memory device, the processing device configured to adjust a scan event threshold for one of the first or second groups of memory cells to a threshold less than a target scan event threshold for the first and second groups of memory cells to distribute scan events in time on the memory device.
    Type: Application
    Filed: May 19, 2020
    Publication date: September 3, 2020
    Inventors: Gianni Stephen Alsasua, Harish Reddy Singidi, Peter Sean Feeley, Ashutosh Malshe, Renato Padilla, JR., Kishore Kumar Muchherla, Sampath Ratnam
  • Patent number: 10755792
    Abstract: Disclosed in some examples, are methods, systems, and machine readable mediums which compensate for read-disturb effects by shifting the read voltages used to read the value in a NAND cell based upon a read counter. For example, the NAND memory device may have a read counter that corresponds to a group of NAND cells (e.g., a page, a block, a superblock). Anytime a NAND cell in the group is read, the read counter may be incremented. The read voltage, Vread, may be adjusted based on the read counter to account for the read disturb voltage.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: August 25, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Harish Reddy Singidi, Kishore Kumar Muchherla, Gianni Stephen Alsasua, Ashutosh Malshe, Sampath Ratnam, Gary F. Besinga, Michael G. Miller