Abstract: A variety of applications can include systems and/or methods of optimizing results from scanning a memory device, where the memory device has stacked multiple reliability specifications. Information about a block of multiple blocks of a memory device can be logged, where the information is associated with a combination of reliability specifications. A refresh of the block can be triggered based on exceeding a threshold condition for the combination of reliability specifications.

Abstract: Systems and methods are disclosed, including maintaining an error recovery data structure for a set of codewords (CWs) in a storage system, the error recovery data structure storing indications that specific CWs are correctable or not correctable by specific error handing (EH) steps of a set of multiple EH steps, and determine an order of EH steps for the storage system based on the error recovery data structure. Maintaining the error recovery data structure can include determining if each CW of the set of CWs is correctable by a specific EH step, storing indications of CWs determined correctable by the specific EH step in the error recovery data structure, and, in response to determining that one or more CW in the set of CWs are not indicated as correctable in the error recovery data structure, incrementing the specific EH step.

Abstract: Systems and methods are disclosed, comprising a memory device comprising multiple groups of memory cells, the groups comprising a first group of memory cells and a second group of memory cells configured to store information at a same bit capacity per memory cell, and a processing device operably coupled to the memory device, the processing device configured to adjust a scan event threshold for one of the first or second groups of memory cells to a threshold less than a target scan event threshold for the first and second groups of memory cells to distribute scan events in time on the memory device.

Abstract: Disclosed in some examples are systems, methods, memory devices, and machine readable mediums for a fast secure data destruction for NAND memory devices that renders data in a memory cell unreadable. Instead of going through all the erase phases, the memory device may remove sensitive data by performing only the pre-programming phase of the erase process. Thus, the NAND doesn't perform the second and third phases of the erase process. This is much faster and results in data that cannot be reconstructed. In some examples, because the erase pulse is not actually applied and because this is simply a programming operation, data may be rendered unreadable at a per-page level rather than a per-block level as in traditional erases.

Abstract: A variety of applications can include use of parity groups in a memory system with the parity groups arranged for data protection of the memory system. Each parity group can be structured with multiple data pages in which to write data and a parity page in which to write parity data generated from the data written in the multiple data pages. Each data page of a parity group can have storage capacity to include metadata of data written to the data page. Information can be added to the metadata of a data page with the information identifying an asynchronous power loss status of data pages that precede the data page in an order of writing data to the data pages of the parity group. The information can be used in re-construction of data in the parity group following an uncorrectable error correction code error in writing to the parity group.

Abstract: Devices and techniques for temperature informed memory refresh are described herein. A temperature counter can be updated in response to a memory device write performed under an extreme temperature. Here, the write is performed on a memory device element in the memory device. The memory device element can be sorted above other memory device elements in the memory device based on the temperature counter. Once sorted to the top of these memory device elements, a refresh can be performed the memory device element.

Abstract: A processing device detects a read operation at a memory device that is directed at a word line group from among multiple word line groups of the memory device. The processing device increments a read counter associated with the word line group based on the read operation being directed at the word line group. The processing device determines the read counter exceeds a read-disturb threshold and performs read-disturb handling on the word line group in response to determining the read counter exceeds the read-disturb threshold.

Abstract: Systems and methods are disclosed, including maintaining an error recovery data structure for a set of codewords (CWs) in a storage system and performing error recovery for the set of CWs using a set of error handing (EH) steps until each CW of the set of CWs are indicated as correctable in the error recovery data structure. The error recovery can include determining if each CW of the set of CWs is correctable by an EH step, storing indications of CWs determined correctable by the EH step in the error recovery data structure, determining if one or more CW in the set of CWs are not indicated as correctable in the error recovery data structure, and, in response to determining that one or more CW in the set of CWs are not indicated as correctable in the error recovery data structure, incrementing the specific EH step.

Abstract: Devices and techniques for a flash memory block retirement policy are disclosed herein. In an example embodiment, a first memory block is provisionally removed from service in response to encountering read errors in the first memory block. Memory pages of the first memory block are tested in a second mode comprising reading memory pages at different read voltages. A raw bit error rate (RBER) or a read window budget (RWB) is determined for memory pages at the different read voltages and the provisionally removed first memory block is returned to service or retired based on the determined RBER or the RWB.

Abstract: Systems and methods are disclosed, comprising a memory device comprising multiple groups of memory cells, the groups comprising a first group of memory cells and a second group of memory cells configured to store information at a same bit capacity per memory cell, and a processing device operably coupled to the memory device, the processing device configured to adjust a scan event threshold for one of the first or second groups of memory cells to a threshold less than a target scan event threshold for the first and second groups of memory cells to distribute scan events in time on the memory device.

Abstract: Devices and techniques for initiating and controlling preemptive idle time read scans in a flash based storage system are disclosed. In an example, a memory device includes a NAND memory array and a memory controller to schedule and initiate read scans among multiple locations of the memory array, with such read scans being preemptively triggered during an idle (background) state of the memory device, thus reducing host latency during read and write operations in an active (foreground) state of the memory device. In an example, the optimization technique includes scheduling a read scan operation, monitoring an active or idle state of host IO operations, and preemptively initiating the read scan operation when entering an idle state, before the read scan operation is scheduled to occur. In further examples, the read scan may preemptively occur based on time-based scheduling, frequency-based conditions, or event-driven conditions triggering the read scan.

Abstract: Disclosed in some examples are systems, methods, memory devices, and machine readable mediums for a fast secure data destruction for NAND memory devices that renders data in a memory cell unreadable. Instead of going through all the erase phases, the memory device may remove sensitive data by performing only the pre-programming phase of the erase process. Thus, the NAND doesn't perform the second and third phases of the erase process. This is much faster and results in data that cannot be reconstructed. In some examples, because the erase pulse is not actually applied and because this is simply a programming operation, data may be rendered unreadable at a per-page level rather than a per-block level as in traditional erases.

Abstract: A variety of applications can include apparatus and/or methods to preemptively detect defect prone memory blocks in a memory device and handle these memory blocks before they fail and trigger a data loss event. Metrics based on memory operations can be used to facililtate the examination of the memory blocks. One or more metrics associated with a memory operation on a block of memory can be tracked and a Z-score for each metric can be generated. In response to a comparison of a Z-score for a metric to a Z-score threshold for the metric, operations can be performed to control possible retirement of the memory block beginning with the comparison. Additional apparatus, systems, and methods are disclosed.

Abstract: A variety of applications can include apparatus and/or methods to preemptively detect detect one memory blocks in a memory device and handle these memory blocks before they fail and trigger a data loss event. Metrics based on memory operations can be used to facilitate the examination of the memory blocks. One or more metrics associated with a memory operation on a block of memory can be tracked and a Z-score for each metric can be generated. In response to a comparison of a Z-score for a metric to a Z-score threshold for the metric, operations can be performed to control possible retirement of the memory block beginning with the comparison. Additional apparatus, systems, and methods are disclosed.

Abstract: A variety of applications can include apparatus and/or methods that provide parity data protection to data in a memory system for a limited period of time and not stored as permanent parity data in a non-volatile memory. Parity data can be accumulated in a volatile memory for data programmed via a group of access lies having a specified number of access lines in the group. A read verify can be issued to selected pages after programming finishes at the end of programming via the access lines of the group. With the programming of the data determined to be acceptable at the end of programming via the last of the access lines of the group, the parity data in the volatile memory can be discarded and accumulation can begin for a next group having a specified number of access lines. Additional apparatus, systems, and methods are disclosed.

Abstract: Disclosed in some examples are NAND devices, firmware, systems, methods, and devices that apply smart algorithms to process ECC errors by taking advantage of excess overprovisioning. In some examples, when the amount of overprovisioned blocks are above a predetermined threshold, a first ECC block error handling mode may be implemented and when the overprovisioned blocks are equal or less than the predetermined threshold, a second mode of ECC block error handling may be utilized.

Abstract: Disclosed in some examples are techniques for handling parity data of a non-volatile memory device with limited cache memory. In certain examples, user data can be programmed into the non-volatile memory of the non-volatile memory device in data stripes, and parity information can be calculated for each individual data stripe within a limited capacity cache of the non-volatile memory device. The individual parity information can be swapped between a swap block of the non-volatile memory and the limited capacity cache as additional data stripes are programmed.

Abstract: Devices and techniques for NAND temperature data management are disclosed herein. A command to write data to a NAND component in the NAND device is received at a NAND controller of the NAND device. A temperature corresponding to the NAND component is obtained in response to receiving the command. The command is then executed to write data to the NAND component and to write a representation of the temperature. The data is written to a user portion and the representation of the temperature is written to a management portion that is accessible only to the controller and segregated from the user portion.

Abstract: A variety of applications can include apparatus and/or methods that provide parity data protection to data in a memory system for a limited period of time and not stored as permanent parity data in a non-volatile memory. Parity data can be accumulated in a volatile memory for data programmed via a group of access lies having a specified number of access lines in the group. A read verify can be issued to selected pages after programming finishes at the end of programming via the access lines of the group. With the programming of the data determined to be acceptable at the end of programming via the last of the access lines of the group, the parity data in the volatile memory can be discarded and accumulation can begin for a next group having a specified number of access lines. Additional apparatus, systems, and methods are disclosed.

Abstract: Devices and techniques for read voltage calibration of a flash-based storage system based on host IO operations are disclosed. In an example, a memory device includes a NAND memory array having groups of multiple blocks of memory cells, and a memory controller to optimize voltage calibration for reads of the memory array. In an example, the optimization technique includes monitoring read operations occurring to a respective block, identifying a condition to trigger a read level calibration based on the read operations, and performing the read level calibration for the respective block or a memory component that includes the respective block. In a further example, the calibration is performed based on a threshold voltage to read the respective block, which may be considered when the threshold voltage to read the respective block is evaluated within a sampling operation performed by the read level calibration.