Abstract: The invention concerns integrated circuits in which a MACRO is embedded in a standard cell array. One level of metal is devoted exclusively to non-local interconnect, and a layer of polysilicon is devoted to local interconnect, thereby saving significant space.

Abstract: The invention concerns integrated circuits in which a MACRO is embedded in a standard cell array. One level of metal is devoted exclusively to non-local interconnect, and a layer of polysilicon is devoted to local interconnect, thereby saving significant space.

Abstract: The invention concerns integrated circuits in which a MACRO is embedded in a standard cell array. One level of metal is devoted exclusively to non-local interconnect, and a layer of polysilicon is devoted to local interconnect, thereby saving significant space.

Abstract: The invention concerns integrated circuits in which a MACRO is embedded in a standard cell array. One level of metal is devoted exclusively to non-local interconnect, and a layer of polysilicon is devoted to local interconnect, thereby saving significant space.

Abstract: The inter-symbol interference problem is reduced by detecting a data sequence indicating when a boost is needed on a ‘short pulse’, usually the first data pulse of the opposite polarity after a string of data pulses of the same value. A data decoder that detects when current compensation is required and an output driver that has the variable drive capability to change the drive current on the short pulse is used to boost the amplitude. The output driver is regulated by a phase locked loop which includes a voltage variable delay digitally controlled voltage variable reference capacitors in the phase locked loop circuit for receiving data from memory that contains the proper capacitor control voltage needed. The time required to charge the capacitor is constant and the delay is slaved to the clock period.

Abstract: The invention concerns integrated circuits in which a MACRO is embedded in a standard cell array. One level of metal is devoted exclusively to non-local interconnect, and a layer of polysilicon is devoted to local interconnect, thereby saving significant space.

Abstract: The invention concerns integrated circuits in which a MACRO is embedded in a standard cell array. One level of metal is devoted exclusively to non-local interconnect, and a layer of polysilicon is devoted to local interconnect, thereby saving significant space.

Abstract: The invention concerns integrated circuits in which a MACRO is embedded in a standard cell array. One level of metal is devoted exclusively to non-local interconnect, and a layer of polysilicon is devoted to local interconnect, thereby saving significant space.

Abstract: The invention concerns integrated circuits in which a MACRO is embedded in a standard cell array. One level of metal is devoted exclusively to non-local interconnect, and a layer of polysilicon is devoted to local interconnect, thereby saving significant space.

Abstract: The invention concerns integrated circuits in which a MACRO is embedded in a standard cell array. One level of metal is devoted exclusively to non-local interconnect, and a layer of polysilicon is devoted to local interconnect, thereby saving significant space.

Abstract: The inter-symbol interference problem is reduced by detecting a data sequence indicating when a boost is needed on a ‘short pulse’, usually the first data pulse of the opposite polarity after a string of data pulses of the same value. A data decoder that detects when current compensation is required and an output driver that has the variable drive capability to change the drive current on the short pulse is used to boost the amplitude. The output driver is regulated by a phase locked loop which includes a voltage variable delay digitally controlled voltage variable reference capacitors in the phase locked loop circuit for receiving data from memory that contains the proper capacitor control voltage needed. The time required to charge the capacitor is constant and the delay is slaved to the clock period.

Abstract: The inter-symbol interference problem is reduced by detecting a data sequence indicating when a boost is needed on a ‘short pulse’, usually the first data pulse of the opposite polarity after a string of data pulses of the same value. A data decoder that detects when current compensation is required and an output driver that has the variable drive capability to change the drive current on the short pulse is used to boost the amplitude. The output driver is regulated by a phase locked loop which includes a voltage variable delay digitally controlled voltage variable reference capacitors in the phase locked loop circuit for receiving data from memory that contains the proper capacitor control voltage needed. The time required to charge the capacitor is constant and the delay is slaved to the clock period.

Abstract: The invention concerns integrated circuits in which a MACRO is embedded in a standard cell array. One level of metal is devoted exclusively to non-local interconnect, and a layer of polysilicon is devoted to local interconnect, thereby saving significant space.

Abstract: The invention concerns integrated circuits in which a MACRO is embedded in a standard cell array. One level of metal is devoted exclusively to non-local interconnect, and a layer of polysilicon is devoted to local interconnect, thereby saving significant space.

Abstract: 3An optimal delay value, usually the mid-delay in the operational window, for the data signal may be retained as a way of shifting the skew of the clock on all data lines at the same time. That delay value may be stored in a memory and converted to a control voltage for controlling a digitally controlled voltage variable delay to adjust the delay for data in a bus. The digitally controlled voltage variable delay contains a number of individual delay units which are selectively activated by the control voltage from the value stored in memory. A phase locked loop is employed to ensure that variations due to voltage, temperature, and processing are minimized.

Abstract: The invention concerns integrated circuits in which a MACRO is embedded in a standard cell array. One level of metal is devoted exclusively to non-local interconnect, and a layer of polysilicon is devoted to local interconnect, thereby saving significant space.

Abstract: A dynamic random access memory (DRAM) segment incorporates at least one shielding conductor spaced from a matrix of memory cells above the substrate and a well formed in the substrate which contains the memory cells. The shielding conductor primarily shields the memory cells from external noise signals created by other conductors. The isolating well primarily shields the memory cells from noise signals created by substrate currents and alpha particles. Among other features the DRAM employs a logically complementary pair of charge storage capacitors and differential sensing to avoid the influence of noise on a single memory capacitor. The shielding conductor is formed by a mesh of conductors or an integral conductor which overlays the matrix of cells and connects to the well. External power supplies and references are also connected to the well and the shielding conductors.

Abstract: A logically complementary pair of charge storage capacitors are employed in each memory cell of an embedded dynamic random access memory (DRAM) segment. The complementary capacitors establish a data bit signal from each cell by a relative difference in charge stored on the capacitors. The adverse influences of noise are reduced or eliminated because the noise will generally equally effect both of the complementary capacitors, as well as complementary bit lines connected to the capacitors. Differential sensing of the bit line signals also avoids the influence of noise. A capacitor reference potential conductor distributes substantially equal capacitor reference voltage to each capacitor to allow each capacitor to charge and discharge more uniformly under the influence of noise.

Abstract: A clock delay circuit which creates control signals relative to a clock signal which vary in relation to inherent variables arising from manufacturing process, temperature and voltage influences on a memory array. The clock delay circuit preferably comprises a pair of spare word lines and a pair of spare bit lines of the memory, each of which extends across the memory array. Signals conducted along the spare word and bit line create a signal which is supplied to a counter and decoder to supply a plurality of control signals having a timing relationship established relative to the clock. The spare word line and spare bit line comprise electrical characteristics affecting signal propagation time similar to a signal propagation time along one of an actual word line or actual bit line, respectively.

Abstract: The plurality of memory cells of a dynamic random access memory (DRAM) are formed in a well of one majority carrier type, and the well is located in a substrate of the other majority carrier type. The well electrically isolates the memory cells from electrical noise signals created by current in the substrate and charged carriers created by alpha particles. The well is connected at multiple spaced-apart locations to a referencing conductor, to maintain the well at a uniform potential in response to noise. The memory cells are formed in a single well, or groups of the memory cells are each formed in a separate well. A shielding conductor, such as the mesh or an integrally continuous layer of metal which is spaced from the memory cells, overlays a matrix of the memory cells and shields then from the effects of noise.