Abstract: A method and apparatus for controlling a threshold of pad input circuits of an integrated circuit such that variations in manufacturing and environment will not substantially change its operating characteristics. The invention uses a very stable reference voltage supply whose output is controlled by a voltage divider circuit to determine the input threshold switching voltage of each pad input circuit. Since the voltage divider can be manufactured more accurately, i.e. with less variation, than the transistors on the integrated circuit and because one reference voltage supply can set the threshold for the entire chip, this invention provides a pad input circuit with accurate and stable input switching characteristics. Additionally the FETs on the inputs of the circuits are matched such that their individual values may vary with the manufacturing process, but as long as they vary in the same proportion, then the switching accuracy and noise immunity will be maintained.

Abstract: The invention concerns a Multi-Chip Module (MCM), which can be viewed as similar to a printed circuit board, but with the conductors interwoven in a 3-dimensional array. In the invention, the conductors are arranged such that both power supply conductors and ground conductors are interwoven around signal conductors, and provide shielding for the signal conductors, thus reducing cross-talk.

Abstract: A voltage variable delay circuit that provides a relatively constant delay independent of operating voltages, temperatures or processing variations is disclosed. The circuit is particularly suited for delay line or oscillator applications. The relatively constant delay is accomplished by accurately controlling the switching speed of each of the complementary series arranged inverter elements used for the delay line or oscillator. The accurate control is provided by first and second high impedance inverters connected to the gate electrode of series arranged inverters. In the delay line application, two similarly fabricated series arranged inverter elements are placed in parallel. One of the series arranged inverters is used as an operating circuit and the other is used as a reference circuit. A clock signal is used to synchronize the reference circuit with a timing network, and a comparator is used to measure the time difference between the reference circuit and the timing network.

Abstract: An electrical connection between a first bus and a second bus on a semiconductor integrated circuit device manufactured using conventional CMOS technology. The first bus has a horn shape which permits a plurality of vias to be arranged in an arc thereon. This arrangement of vias facilitates permitting the current to flow substantially evenly between a first bus and a second bus.

Abstract: A high speed, D-type flip-flop is implemented using eight complementary metal-oxide semiconductor (CMOS) tristate inverters. The flip-flop includes both D and D/ data input terminals and parallel data paths from the data input terminals to Q and Q/ output terminals. The improved circuit design realizes higher operating speed than prior CMOS flip-flops by eliminating the inverter delays present in single path flip-flops and providing only two gates in the data paths between the input and output terminals.

Abstract: A high density arrangement of input/output pad cells for general application, but especially useful in non-pad limited design because it conserves substrate area that is not needed for pad cells. The pad cells have their transistors, protection diodes and integrated pull up resistors located in a linear array between the physical pads where the electrical leads make contact. Each pad cell has a bank of N-FETs on one of its lateral sides and a bank of P-FETs on its opposite lateral side. By interchanging the location of the banks of N-FETs and P-FETs of adjacent pad cells relative to the physical pad, a high density arrangement is achieved that is not prone to forming parasitic thyristors or the latch-up problem associated with such parasitic thyristors. The pad cells are shielded from noise pulses and surges on their outer perimeter by a two level power bus, and on their inner perimeter by a similar two level power bus.

Abstract: An electronic circuit for converting trinary level input signals on a first line into binary level signals on two or more output lines using contemporary CMOS field effect transistor integrated circuits. According to one embodiment, conversion is accomplished using two CMOS inverters each asymmetrically configured to exhibit transconductances which differ by a factor in excess of 5. In another form, the circuit provides hysteresis through positive feedback to limit binary output state perturbations attributable to trinary signal level input noise. The invention also encompasses the use of decode logic and logically combined delay elements to eliminate "glitches" and facilitate selective enablement of the decoded states representing the intermediate of the trinary input levels.

Abstract: An architecture for the input/output circuits and pads of a gate array integrated circuit product functionally configured during the formation and connection of one or more metallization layers. In a preferable practice of the invention, cells of first impurity type and second impurity type transistors are formed in respective parallel but spaced apart rows along the chip perimeters with a pad definition region lying therebetween. Successively adjacent cell transistors are contiguous as to source regions and are electrically separable by cell gate isolation. Preferably, the individual cell transistors have annular gate electrodes with centrally disposed and also fully isolatable drain regions.

Abstract: An output driver for reducing current spikes in an output comprising three transistors connected between an output node and a reference voltage terminal. The first transistor is responsive to an input data signal, the second transistor is responsive to a first feedback signal from the output, and the third transistor is responsive to a second feedback signal from the output.

Abstract: A CMOS gate isolated gate array configured with a single polysilicon layer and preferably two metallization layers, wherein the cell pitch is equal to the first and second metallization pitches by referencing the metallization layers, contacts and vias to a grid, and referencing the polysilicon layer to a half grid. Further refinements include the use of channel regions between parallel and adjacent chains of complementary transistors, wherein the width of the channel is equal to three times the pitch of the cell. In another form, a base set of the gate array includes diffused resistors in the channel regions suitable for matching discretionary interconnection.

Abstract: A high frequency integrated circuit channel capacitor structure comprised of interdigitated field effect transistor gate electrodes and source/drain regions of minimum dimension and respective common connection. The multiplicity of parallel connected capacitive regions between the polysilicon gate electrode and a channel region in the substrate provide precisely controlled capacitors with exceptionally low resistance. Metallization contacts to the gate polysilicon and source/drain regions at each interleaved pattern, together with minimum channel length dimensions, minimizes the capacitive resistance. A CMOS configuration is also feasible.

Abstract: A common cell for use as an input/output circuit in a CMOS integrated circuit having a P-channel transistor structure having a plurality of individual P-channel transistors, an N-channel transistor structure having a plurality of individual N-channel transistors and an I/O pad. The sources, drains and gates of the individual P-channel and N-channel transistors are connected to terminals. The various terminals and the I/O pad may be selectively connected in various ways to form various input/output circuits, as desired.

Abstract: A circuit for adding a function such as a test mode to an integrated circuit includes a pad for receiving an enabling voltage when the added function is to be enabled, and a semiconductor device having an input terminal connected to the pad, a reference terminal for receiving a reference voltage, a diode junction having one side connected to the input terminal and its other side connected to the reference terminal for applying a bias across the diode junction, and an output terminal controlled by the diode junction such that current flows therethrough when the diode junction is forward biased, and does not flow when said diode junction is reversed biased.

Abstract: A CMOS inverter circuit wherein the input device is formed with a p-well as the back-gate and is adapted to receive negative going input signals at the p-well. The gate of the input device is connected to a bias supply set just above the threshold for the input device. With the input signal voltage at 0, the inverter is on, and the output voltage is near 0. As the input signal voltage goes negative, the threshold of the input device increases due to the back-gate bias effect, and it turns off, causing the output voltage to go positive.