Abstract: A method of connecting a first and second circuit device includes providing a first circuit device having a first main area and a second circuit device having a second and a third main area. A spacer device is disposed on one of the first and second circuit devices to ensure a predetermined spacing between the first and second circuit devices. An adhesive is applied to at least one of the first main area and the second main area and the first and second circuit devices are aligned and joined. The adhesive is then cured.

Abstract: A method for forming printed re-routing for wafer level packaging, especially chip size packaging. The method includes forming a contact layer on a semiconductor die, printing a conductive redistribution structure on the contact layer, and etching the contact layer of the die by using the conductive redistribution structure as a self-aligning mask.

Abstract: A contact connection between a semiconductor chip and a substrate has a conductive adhesive extending between each contact of the chip and the substrate. The conductive adhesive includes a matrix component, a filler component, a hardener component and at least one decomposable component so that after curing at a curing temperature T1, the adhesive can be decomposed either by applying thermal energy at a temperature T2>T1 or by radiation so that the two contact surfaces can be separated smoothly. After separation the purposes of replacing a defective semiconductor chip, a second chip can be mechanically connected by applying the adhesive and curing it.

Abstract: A method for fabricating a structure on an integrated circuit (IC) wafer, includes providing a material onto a surface of the wafer and shaping the material to have a shape corresponding to the structure. The method can also include removing a remaining portion of the material, depositing a seed layer onto the wafer and the material, and depositing a photoresist on the wafer. In addition, the method can include depositing a metal layer on top of the seed layer, removing the photoresist, etching the seed layer, and etching the material. The resulting structure is usable as a compression stop, a compliant element or a rerouting layer or a combination thereof.

Abstract: Laser Programming of Integrated Circuits. The invention relates to the laser adjustment or laser programming of laser fuses of an integrated circuit on a chip, with laser light, the integrated circuit having a plurality of laser fuses and being connected to a plurality of contact pads on the chip, and the chip being covered with a polymer layer which has at least windows on the plurality of contact pads, and comprising at least one wiring interconnect on the polymer layer which is electrically connected to at least one of the plurality of contact pads and ends at a predetermined location on a surface of the chip.

Abstract: The present invention provides a method of producing semiconductor chips (1a, 1b, 1c; 1a′, 1b′, 1c′) with a protective chip-edge layer (21″, 22″), in particular for wafer level packaging chips, with the steps of: preparing a semiconductor wafer (1); providing trenches (21, 22) in the semiconductor wafer to establish chip edges on a first side of the semiconductor wafer (1); filling the trenches (21, 22) with a protective agent (21′; 22′); grinding back the semiconductor wafer (1) from a second side of the semiconductor wafer (1), which is opposite from the first side, to expose the trenches (21, 22) filled with the protective agent (21′; 22′); and cutting through the trenches (21, 22) filled with the protective agent (21′; 22′), so that the protective chip-edge layer (21″, 22″) comprising the protective agent (21′, 22′) remains on the chip edges.

Abstract: A method for fabricating a structure on an integrated circuit (IC) wafer, includes providing a material onto a surface of the wafer and shaping the material to have a shape corresponding to the structure. The method can also include removing a remaining portion of the material, depositing a seed layer onto the wafer and the material, and depositing a photoresist on the wafer. In addition, the method can include depositing a metal layer on top of the seed layer, removing the photoresist, etching the seed layer, and etching the material. The resulting structure is usable as a compression stop, a compliant element or a rerouting layer or a combination thereof.

Abstract: The invention creates a method for connection of circuit units (101a-10n) which are arranged on a wafer (100), in which the wafer (100) is fitted to a first film (102a), the wafer (100) is sawn such that the circuit units (101a-101n) which are arranged on the wafer (100) are separated, the functional circuit units (101d) are picked up by means of a handling device (101) and are placed down on a second film (102b) by means of the handling device (103), so as to produce a separation distance which can be predetermined between connection contacts of the circuit units (101d).

Abstract: An electronic component has a plurality of chips which are stacked one above the other and contact-connected to one another. To form this component, a first planar chip arrangement is provided with the functional chips spaced apart from one another in a grid and with a filling material in the spaces between the chips to form an insulating holding frame that fixes the chips, the frame has chip-dedicated contact-connecting elements that serve for the electrical contact-connection to another chip of another chip arrangement and each chip has dedicated electrically conductive strips. At least one additional planar chip arrangement is formed by the same method as the first planar chip arrangement and is then stacked on the first planar chip arrangement so that the two chip arrangements lie one above the other and the respective contact-connecting elements of the two chip arrangements are connected to one another for electrical chip-to-chip contact-connection.

Abstract: A process for producing a component module comprising a module carrier and a plurality of components with which contact is made on the latter, comprising the following steps:

Abstract: A process for producing a semiconductor chip having contact elements protruding on one chip side within the context of wafer level packaging, the chip side provided with the contact elements being coated with a covering compound forming a protective layer, from which the protruding contact element project.

Abstract: A semiconductor structure and a method for forming the semiconductor structure, including a semiconductor chip and a conductive layer disposed over a portion of the chip, the conductive layer having a portion that extends beyond an edge of the chip. The chip includes a device, which can be an integrated circuit or a micro-mechanical device. The structure can also include a front layer extending beyond the edge of the chip, the conductive layer being disposed on the front layer.

Abstract: A semiconductor structure includes a semiconductor substrate and a compliant interconnect element disposed on a first surface of the substrate. The compliant interconnect element defines a chamber between the first surface of the substrate and a surface of the compliant interconnect element. The compliant interconnect element can be a compliant layer. The compliant layer can be formed of a polymer, such as silicone. A conductive layer can be disposed on the compliant layer, in contact with a contact pad on the semiconductor substrate. A method for forming a semiconductor structure includes providing a semiconductor substrate and providing a compliant interconnect element on a first surface of the substrate, so that the compliant interconnect element defines a chamber between the compliant interconnect element and the first surface of the substrate.

Abstract: An electronic configuration has a first surface with electrical contacts for electrical bonding. The configuration includes at least one flexible elevation made of an insulating material that is arranged on the first surface. The flexible elevation has at least one recess and the surface of the flexible recess is at least partially covered with an electrically conductive material to form one of the electrical contacts.

Abstract: An electronic component having at least one semiconductor chip, a rewiring layer connected to the semiconductor chip, and a printed circuit board associated with the rewiring layer. The rewiring layer is provided with flexible contacts that correspond with contact faces of the printed circuit board, and the rewiring layer is solidly connected to the printed circuit board via a flat intermediate layer. A method for producing the electronic component is described.

Abstract: An electronic component has an electronic circuit and a rubber-elastic elevation. The rubber-elastic elevation is formed of an insulating rubber-elastic material disposed on a surface of the electronic component and has a conductive land on its crest. The rubber-elastic elevation also has on its sloping side or in its volume a conduction path between the land and the electronic circuit.

Abstract: The invention proposes a semiconductor component with a semiconductor chip having a first main side with at least one contact pad thereon. A protective layer is applied on the first main side such that a clearance is provided around the contact pad. It is possible for the semiconductor component to be connected to a substrate using flip-chip bonding. Elevations that are connected to contact pads via conductor runs located on the protective layer are provided on the first main side. The elevations may be produced either by printable materials or by repeated electrodepositing of the ends of the conductor tracks lying opposite the contact pads.

Abstract: Electronic component, in particular a chip, which can be electrically bonded by means of a plurality of contacts provided on the component to mating contacts provided on a carrier, each contact (9) having a raised elastic base (3) of a conductive material which is connected to a lead (7) on the component side, and to which there is applied on the upper side a metallic cap-like contact covering (6), only partially covering the base (3).

Abstract: A method for forming printed re-routing for wafer level packaging, especially chip size packaging. The method includes forming a contact layer on a semiconductor die, forming a conductive redistribution structure on the contact layer, and etching the contact layer of the die by using the conductive redistribution structure as a self-aligning mask. The present method significantly decreases the complexity and costs for generating redistribution structures in wafer level packaging by discarding expensive processes for photolithography and plating. Furthermore, using the redistribution structures as a self-aligning mask improves alignment and reduces the number of processes required, leading to greater production optimization and efficiency.

Abstract: An electronic component with at least one semiconductor chip and a wiring layer are described. The wiring layer has elastic contact elements of low mechanical strength in the spatial directions x, y and z, which can be electrically connected to corresponding contact terminal areas of a printed circuit board. The semiconductor chip or the wiring layer additionally has at least two spacers for the mechanical connection to a printed circuit board. A method for producing the electronic component is also described.