Patents by Inventor Harry Hedler

Harry Hedler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070120268
    Abstract: An electronic component includes a substrate having contacts and a chip having contacts and a passivation layer disposed on an active side of the chip. The active side of the chip is mounted on a first surface of the substrate by flip chip technology such that the contacts of the chip are electrically connected to the contacts of the substrate by means of connecting elements. Elastic elevations are disposed between the contacts of the chip and the contacts of the substrate and an underfiller is disposed in an intermediate space between the chip and the substrate and between the elastic elevations. The underfiller and the elastic elevations have substantially the same modulus of elasticity.
    Type: Application
    Filed: January 13, 2006
    Publication date: May 31, 2007
    Inventors: Roland Irsigler, Harry Hedler, Bernd Goller, Gerald Ofner
  • Patent number: 7221053
    Abstract: The present invention relates to an integrated device comprising an electronic circuit chip, a solder contact structure to provide contact to the electronic circuit chip and an elastic contact structure to provide contact to the electronic circuit chip, wherein the solder contact structure and the elastic contact structure are arranged on a contacting surface of the integrated device.
    Type: Grant
    Filed: March 21, 2005
    Date of Patent: May 22, 2007
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Meyer, Harry Hedler, Stephan Dobritz
  • Patent number: 7217646
    Abstract: Method for connecting an integrated circuit to a substrate and corresponding circuit arrangement The present invention provides a method for connecting an integrated circuit (C1), in particular a chip or a wafer or a hybrid, to a substrate (C2), which has the following steps: provision of a first electrical contact structure (KF1, BP, LB; KF1, BP?) on a first main area (HF1) of the integrated circuit (C1); provision of a corresponding second electrical contact structure (KF2) on a second main area (HF2) of the substrate (C2); at least one of the contact structures, the first electrical contact structure (KF1, BP, LB; KF1, BP?) or the second electrical contact structure (KF2), being elastic; placement of the first electrical contact structure (KF1, BP, LB; KF1, BP?) onto the corresponding second electrical contact structure (KF2), so that both are in electrical contact and under mechanical compression pressure (P); and connection of a region of the main area (HF1) surrounding the first electrical contact struc
    Type: Grant
    Filed: June 15, 2005
    Date of Patent: May 15, 2007
    Assignee: Infineon Technologies AG
    Inventors: Harry Hedler, Thorsten Meyer
  • Publication number: 20070096249
    Abstract: A three-dimensionally integrated electronic assembly includes a substrate that includes active circuitry formed therein. At least one electronic component (e.g., an integrated circuit chip, active component, passive component, active assembly, and/or passive assembly) is mounted on the substrate. At least one redistribution connection is disposed between the substrate and at least one electronic component. Each electronic component is electrically coupled to the substrate and/or another electronic component mounted on the substrate by means of the redistribution connection.
    Type: Application
    Filed: August 31, 2006
    Publication date: May 3, 2007
    Inventors: Heiko Roeper, Johannes Hankofer, Harry Hedler, Armin Kohlhase
  • Patent number: 7211472
    Abstract: A method for producing a multi-chip module having application of at least one contact elevation onto a substrate, application and patterning of a rewiring device onto the substrate and the at least one contact elevation with provision of a contact device on the at least one contact elevation, application of a semiconductor chip onto the substrate with electrical contact-connection of the rewiring device; application of an encapsulating device that is not electrically conductive onto the semiconductor chip, the substrate, the rewiring device and the at least one contact elevation, the contact device on the at least one contact elevation at least touching a first surface of the encapsulating device; and repetition at least once of at least the first two steps, the first surface of the encapsulating device serving as a substrate and the correspondingly produced rewiring device making electrical contact with the contact device of the at least one contact elevation of the underlying plane.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: May 1, 2007
    Assignee: Infineon Technologies AG
    Inventors: Harry Hedler, Roland Irsigler
  • Patent number: 7211451
    Abstract: A process for producing a component module comprising a module carrier and a plurality of components with which contact is made on the latter, comprising the following steps: arranging separated components on a surface-adhesive film at a predefined contact-specific spacing from one another, embedding the components in a flexible material in order to form a flexible holding frame which holds the components, pulling off the film, producing contact-making elements on the exposed side of the components, performing a functional test of the components and, if necessary, repair and/or replacement of components, and fixing and making contact with the components held in the holding frame on the module carrier.
    Type: Grant
    Filed: November 18, 2002
    Date of Patent: May 1, 2007
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Meyer, Gerd Frankowsky, Harry Hedler, Barbara Vasquez, Roland Irsigler
  • Patent number: 7208345
    Abstract: A first reconstituted wafer is formed, followed by a first redistribution layer. In parallel, a second reconstituted wafer is formed. The second reconstituted wafer is diced along a gap such that individualized embedded chips are formed having tilted sidewalls defining an angle of more than 90 degrees with respect to the active surface of the reconstituted wafer. The embedded chips are placed with the backside on an active surface of the first reconstituted wafer on the first redistribution layer. Afterwards, a second redistribution layer is formed on the active surface of the embedded chips and tilted sidewalls wherein the second redistribution layer connects contact pads of the second chips with the first redistribution layer.
    Type: Grant
    Filed: May 11, 2005
    Date of Patent: April 24, 2007
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Meyer, Harry Hedler
  • Publication number: 20070084944
    Abstract: Method and apparatus for aligning components of a device. In one embodiment a method of aligning includes providing a device having a surface on which a number of adjusting structures is provided in predetermined regions, wherein each of the adjusting structures of the device has a first region having a first wettability and a second region having a second wettability, wherein the second wettability is lower than the first wettability. A number of liquid droplets is provided in a fixed arrangement which corresponds to the arrangement of the adjusting structures in the predetermined regions of the device. The device is placed on the liquid droplets in such a way that each of the droplets abuts at least partially on the inner region of the corresponding adjusting structure of the device in such a way that the device is aligned with regard to the arrangement of the number of droplets.
    Type: Application
    Filed: October 14, 2005
    Publication date: April 19, 2007
    Inventors: Harry Hedler, Roland Irsigler, Thorsten Meyer
  • Publication number: 20070075122
    Abstract: The present invention relates to a method for fabricating a device module having the steps of providing an integrated device in a Ball Grid Array package wherein the integrated device has a solder contact elevated from a surface of the integrated device, providing a printed circuit board having a contact pad, applying a conductive adhesive on at least one of the solder ball contact and the contact pad, arranging the integrated device on the printed circuit board such that the solder ball contact structure is connected to the contact pad by means of the conductive adhesive.
    Type: Application
    Filed: September 30, 2005
    Publication date: April 5, 2007
    Inventors: Laurence Singleton, Thorsten Meyer, Harry Hedler
  • Publication number: 20070066139
    Abstract: An electronic device includes a first semiconductor device and a second semiconductor device mounted over the first semiconductor device. An encapsulation material surrounds the first and second semiconductor devices so that the first and second semiconductor devices are embedded within a molded package. A plug connector extends from the molded package and is electrically coupled to at least one of the first and second semiconductor devices.
    Type: Application
    Filed: August 31, 2006
    Publication date: March 22, 2007
    Inventors: Heiko Roeper, Johannes Hankofer, Armin Kohlhase, Elard Kamienski, Harry Hedler
  • Publication number: 20070032059
    Abstract: A method of manufacturing a semiconductor structure having a wafer through-contact and a corresponding semiconductor structure This invention provides a method of manufacturing a semiconductor structure having a wafer through-contact and a corresponding semiconductor structure.
    Type: Application
    Filed: August 2, 2005
    Publication date: February 8, 2007
    Inventors: Harry Hedler, Roland Irsigler
  • Publication number: 20070023886
    Abstract: The present invention relates to a method and apparatus for producing a chip arrangement. In one embodiment, the method includes providing a first chip having an electrically operable structure, of providing at least one through-via through the first chip, and of arranging at least one bond wire through the through-via in the first chip.
    Type: Application
    Filed: July 5, 2006
    Publication date: February 1, 2007
    Inventors: Harry Hedler, Roland Irsigler
  • Publication number: 20060270109
    Abstract: Manufacturing method for an electronic component assembly and corresponding electronic component assembly The present invention provides a manufacturing method for an electronic component assembly and to a corresponding electronic component assembly.
    Type: Application
    Filed: May 31, 2005
    Publication date: November 30, 2006
    Inventors: Stephan Blaszczak, Martin Reiss, Bernd Scheibe, Steffen Kroehnert, Knut Kahlisch, Ingolf Rau, Harry Hedler, Soo Park
  • Publication number: 20060258044
    Abstract: A first reconstituted wafer is formed, followed by a first redistribution layer. In parallel, a second reconstituted wafer is formed. The second reconstituted wafer is diced along a gap such that individualized embedded chips are formed having tilted sidewalls defining an angle of more than 90 degrees with respect to the active surface of the reconstituted wafer. The embedded chips are placed with the backside on an active surface of the first reconstituted wafer on the first redistribution layer. Afterwards, a second redistribution layer is formed on the active surface of the embedded chips and tilted sidewalls wherein the second redistribution layer connects contact pads of the second chips with the first redistribution layer.
    Type: Application
    Filed: May 11, 2005
    Publication date: November 16, 2006
    Applicant: Infineon Technologies AG
    Inventors: Thorsten Meyer, Harry Hedler
  • Publication number: 20060244109
    Abstract: A method for fabricating an integrated circuit connection region includes application of a dielectric to an integrated circuit with a connection region, application of a corrodible metalization layer to the dielectric, application of a protection device to the metalization layer, and removal of the protection device in a region around the connection region.
    Type: Application
    Filed: May 15, 2006
    Publication date: November 2, 2006
    Inventors: Harry Hedler, Roland Irsigler, Thorsten Meyer, Barbara Vasquez
  • Publication number: 20060220262
    Abstract: A stacked die package includes a substrate or interposer board that includes a contact area on a top surface and landing pads surrounding the contact area. Solder pads are disposed on an opposite side of the substrate. The solder pads are electrically connected with the landing pads by inner board wiring. A reconstituted die, which includes a die surrounded by a frame, is mounted over the substrate. A top die is mounted over the reconstituted die. Both the reconstituted die and the top die are electrically connected to the substrate, e.g., by wire bonds.
    Type: Application
    Filed: April 4, 2005
    Publication date: October 5, 2006
    Inventors: Torsten Meyer, Harry Hedler
  • Publication number: 20060208357
    Abstract: The present invention relates to an integrated device comprising an electronic circuit chip, a solder contact structure to provide contact to the electronic circuit chip and an elastic contact structure to provide contact to the electronic circuit chip, wherein the solder contact structure and the elastic contact structure are arranged on a contacting surface of the integrated device.
    Type: Application
    Filed: March 21, 2005
    Publication date: September 21, 2006
    Inventors: Thorsten Meyer, Harry Hedler, Stephan Dobritz
  • Publication number: 20060177964
    Abstract: The present invention provides a semiconductor module having: a semiconductor device (10) having a contact device (11) for making electrical contact with a connection device (17; 20) via a rewiring device (15, 15?, 15?); and a carrier device (12, 13, 14) for mechanically coupling the semiconductor device (10) to a connection device (17), the carrier device (12, 13, 14) having a gradient between a first modulus of elasticity at the semiconductor device (10) and a second, higher modulus of elasticity at the connection device (17; 20). The present invention likewise provides a method for producing a semiconductor module.
    Type: Application
    Filed: February 28, 2006
    Publication date: August 10, 2006
    Inventors: Harry Hedler, Roland Irsigler, Thorsten Meyer
  • Patent number: 7087512
    Abstract: A method for fabricating an integrated circuit connection region includes application of a dielectric to an integrated circuit with a connection region, application of a corrodible metalization layer to the dielectric, application of a protection device to the metalization layer, and removal of the protection device in a region around the connection region.
    Type: Grant
    Filed: August 15, 2003
    Date of Patent: August 8, 2006
    Assignee: Infineon Technologies AG
    Inventors: Harry Hedler, Roland Irsigler, Thorsten Meyer, Barbara Vasquez
  • Publication number: 20060163717
    Abstract: The present invention provides a method for connection of an integrated circuit (1), in particular of a chip, a wafer or a hybrid, to a substrate (10), which has the following steps: provision of an elastic intermediate layer (5) on the integrated circuit (1) and/or the substrate (10); structuring of the elastic layer (5) in raised areas (5a) and recessed areas (5b); and connection of the substrate (10) and of the integrated circuit (1) via the structured elastic intermediate layer (5). The invention likewise provides a corresponding circuit arrangement.
    Type: Application
    Filed: July 20, 2005
    Publication date: July 27, 2006
    Inventors: Harry Hedler, Anton Legen