Abstract: A vertical thyristor memory array including: a vertical thyristor memory cell, the vertical thyristor memory cell including: a p+ anode; an n-base located below the p+ anode; a p-base located below the n-base; a n+ cathode located below the p-base; an isolation trench located around the vertical thyristor memory cell; an assist gate located in the isolation trench adjacent the n-base wherein an entire vertical height of the assist gate is positioned within an entire vertical height of the n-base.

Abstract: Operations with reduced current overall are performed on single thyristor memory cells forming a volatile memory cell cross-point array. An operation is performed on at least one memory cell in a first group of memory cells out of a plurality of groups of memory cells coupled to a line. A first voltage is applied across the first group of memory cells for the operation and a lower second voltage is applied across the other groups of memory cells. The first voltage is then applied across a second group of memory cells while the second voltage is applied across the other groups including the first group of memory cells. These steps may repeated until the operations covers all the groups.

Abstract: Single thyristor memory cells form a volatile memory array. A sense amplifier reads the state of the thyristor in a selected memory cell against a dummy cell through precharged lines.

Abstract: Memory cells are formed with vertical thyristors to create a volatile memory array. Power consumption in such arrays is reduced or controlled with various techniques including encoding the data stored in the arrays.

Abstract: A volatile memory array using vertical thyristors is disclosed together with methods of operating the array to read, write, retain and refresh data stored therein.

Abstract: A memory cell based upon thyristors for an SRAM integrated circuit can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM cells. Special circuitry provides lowered power consumption during standby.

Abstract: An OTP (One-Time Programmable) memory cell in an array has a programming MOSFET and symmetrically placed access transistors on either side of the programming MOSFET. The balanced layout of the memory cell improves photolithographic effects with a resulting improved process results. Results of programming the memory cell is also improved.

Abstract: A vertical thyristor memory array including: a vertical thyristor memory cell, the vertical thyristor memory cell including: a p+ anode; an n-base located below the p+ anode; a p-base located below the n-base; a n+ cathode located below the p-base; an isolation trench located around the vertical thyristor memory cell; an assist gate located in the isolation trench adjacent the n-base wherein an entire vertical height of the assist gate is positioned within an entire vertical height of the n-base.

Abstract: A volatile memory array using vertical thyristors is disclosed together with methods of operating the array to read data from and write data to the array.

Abstract: Memory arrays of vertical thyristor memory cells with SiGe base layers are described. The composition of the SiGe can be constant or varied depending upon the desired characteristics of the memory cells. The memory cells allow a compact structure with desirable low voltage operations.

Abstract: An MTP (Many Times Programmable) memory cell for integrated circuit memory arrays is described. The cell includes an MTP device and a thyristor interconnected so that the MTP device triggers the thyristor to turn on during a Read or Verify operation. The difference in threshold voltages between a data memory cell and a reference memory cell is used to determine the information in the data memory cell. Different memory cell structures may be constructed for different memory array requirements.

Abstract: Memory cells are formed with vertical thyristors to create a volatile memory array. Power consumption in such arrays is reduced or controlled with various techniques including encoding the data stored in the arrays.

Abstract: Isolation between vertical thyristor memory cells in an array is improved with isolation regions between the vertical thyristor memory cells. The isolation regions are formed by electrically isolating cores surrounded by insulating material, such as silicon dioxide, in trenches between the memory cells. The electrically isolating cores may be tubes of air or conducting rods. Methods of constructing the isolation regions in a processes for manufacturing vertical thyristor memory cell arrays are also disclosed.

Abstract: Methods and systems for reducing electrical disturb effects between thyristor memory cells in a memory array are provided. Electrical disturb effects between cells are reduced by using a material having a reduced minority carrier lifetime as a cathode line that is embedded within the array. Disturb effects are also reduced by forming a potential well within a cathode line, or a one-sided potential barrier in a cathode line.

Abstract: A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM.

Abstract: A volatile memory array using vertical thyristors is disclosed together with methods of operating the array to read data from and write data to the array.

Abstract: A method of programming one-time programmable (OTP) memory cells in an array is described. Each memory cell has a MOSFET programming element and a MOSFET pass transistor, the MOSFET pass transistor having a gate electrode over a channel region between two source/drain regions, and the MOSFET programming element having a gate electrode over a channel region contiguous to a source/drain region either part of, or connected to, one of the two source/drains associated with the MOSFET pass transistor. The other source/drain region of the MOSFET pass transistor is coupled to a bit line. The memory cell is programmed by setting a first voltage of a first polarity on the gate electrode of the pass transistor to electrically connect the source/drain regions of the pass transistor; setting a second voltage of the first polarity on the gate electrode of the programming element; and setting a third voltage of a second polarity on the bit line.

Abstract: An OTP (One-Time Programmable) memory cell in an array has a programming MOSFET and symmetrically placed access transistors on either side of the programming MOSFET. The balanced layout of the memory cell improves photolithographic effects with a resulting improved process results. Results of programming the memory cell is also improved.

Abstract: A vertical thyristor memory array including: a vertical thyristor memory cell, the vertical thyristor memory cell including: a p+ anode; an n-base located below the p+ anode; a p-base located below the n-base; a n+ cathode located below the p-base; an isolation trench located around the vertical thyristor memory cell; an assist gate located in the isolation trench adjacent the n-base wherein an entire vertical height of the assist gate is positioned within an entire vertical height of the n-base.

Abstract: A volatile memory array using vertical thyristors is disclosed together with methods of fabricating the array.