Abstract: The present digital synchronous circuit includes a clock generating circuit for outputting a plurality of clock signals CLK1 to CLKn, a plurality of first latch circuits, each for receiving an input data signal DIN at a data input terminal and for receiving a corresponding clock signal at a clock input terminal, a plurality of second latch circuits, each for latching, in response to the receipt of a control signal LC, an output signal from a corresponding first latch circuit, and a control circuit for receiving input data signal DIN to generate control signal LC. Control circuit outputs control signal LC after a delay of a prescribed period of time after the change in input data signal DIN. As a result, the adverse influence of the meta-stable state that occurs when sampling an asynchronous input data signal DIN is avoided, while at the same time, the chip size and power consumption are limited.

Abstract: A digital synchronization circuit 1000 according to the present invention includes: a polyphase clock generation circuit outputting a plurality of clock signals having the sane frequency and different phases; a selection circuit selecting and outputting one of the plurality of clock signals in accordance with the selection signal; and a selection control circuit outputting a selection signal in accordance with a clock selection signal and the plurality of clock signals. The timing at which a value of the selection signal changes from the first value to the second value is in the period in which potential levels of the clock signals respectively represented by the first and second values are the same. Thus, an output clock signal without any hazard is output which is in synchronization with an input data signal of a plurality of clock signals.

Abstract: A house code assigning device includes a communication unit for sending a command for requesting transmission of a house code to electronic equipment included in a system and for receiving a house code from the electronic equipment, a verification unit for verifying whether or not a house code received by the communication unit is correct and for outputting a verification result showing whether or not the house code received by the communication unit is correct, and a display control unit for controlling a light emitting unit according to the verification result from the verification unit.

Abstract: It is an object to automatically and rapidly assign a logical network address to a terminal connected newly to a network. A data holding section (14) of a network terminal (10) holds a value of a self-device address (DA) and information indicating whether the DA has a maximum value in the same network address (NA) or not. When a terminal connected newly to a network transmits address request data for requesting to give an address onto the network, a terminal having the maximum DA at that time transmits DA grant data indicative of a self-address (that is, the maximum DA) as an acknowledgement thereof. A new terminal receiving the DA grant data sets a greater value than the maximum DA to be the self-DA.

Abstract: The semiconductor integrated circuit includes a first transistor which flows a current from a high voltage source to a first node, a second transistor which flows a current from the first node to a low voltage source. Furthermore, a first inverter receives an input signal and drives the first node based on this input signal, and a second inverter drives a second node based on a voltage of the first node.

Abstract: A driver circuit generates two control signals that change from low to high as an input signal changes from high to low, and change from high to low as the input signal changes from low to high. The driver circuit also generates another two control signals that change from high to low as the input signal changes from high to low, and change from low to high as the input signal changes from low to high. The driver circuit applies these four control signals to gate terminals of four MOS transistors. Timings of logical level changes of these four control signals are controlled so as to generate a period in which the four MOS transistors are simultaneously turned on or off.

Abstract: A semiconductor integrated circuit includes inverters and a PMOS transistor which are disposed for a first signal, and inverters and a PMOS transistor which are disposed for a second signal substantially complementary to the first signal. By the transistors, potentials of signal lines are driven. A transistor for 1.8 V is used for each of the transistors and the inverters at the rear stage. A transistor for 3.3 V is used for each of the inverters at the front stage. With the configuration, the complementary signals are transmitted at optimum timings.

Abstract: A semiconductor integrated circuit includes a differential amplifier, a common level detection circuit which detects a common level of input signals A and B, and a bias generation circuit which generates a bias voltage to be applied to a gate terminal of a MOS transistor that is a constant-current power source of the differential amplifier based on the detected level.

Abstract: A driver circuit generates two control signals that change from low to high as an input signal changes from high to low, and change from high to low as the input signal changes from low to high. The driver circuit also generates another two control signals that change from high to low as the input signal changes from high to low, and change from low to high as the input signal changes from low to high. The driver circuit applies these four control signals to gate terminals of four MOS transistors. Timings of logical level changes of these four control signals are controlled so as to generate a period in which the four MOS transistors are simultaneously turned on or off.

Abstract: The semiconductor integrated circuit includes a first transistor which flows a current from a high voltage source to a first node, a second transistor which flows a current from the first node to a low voltage source. Furthermore, a first inverter receives an input signal and drives the first node based on this input signal, and a second inverter drives a second node based on a voltage of the first node.

Abstract: A semiconductor integrated circuit includes a differential amplifier, a common level detection circuit which detects a common level of input signals A and B, and a bias generation circuit which generates a bias voltage to be applied to a gate terminal of a MOS transistor that is a constant-current power source of the differential amplifier based on the detected level.

Abstract: A digital data transmission system for transmitting digital data, a frame pulse signal, and a clock using a required minimum number of signal lines and with a simple circuit structure is provided. A signal separation circuit (46) that receives a multiple clock (CKFP) which is a frame pulse signal (FP) multiplexed with a clock (CK) includes a clock recovery circuit (47) for reproducing a recovered clock (RCK) by synchronization with the multiple clock (CKFP) using a synchronization loop, and a frame pulse signal separation circuit (48) for separating a recovered frame pulse signal (RFP) from the multiple clock (CKFP) on the basis of the recovered clock (RCK).

Abstract: A semiconductor integrated circuit includes inverters and a PMOS transistor which are disposed for a first signal, and inverters and a PMOS transistor which are disposed for a second signal substantially complementary to the first signal. By the transistors, potentials of signal lines are driven. A transistor for 1.8 V is used for each of the transistors and the inverters at the rear stage. A transistor for 3.3 V is used for each of the inverters at the front stage. With the configuration, the complementary signals are transmitted at optimum timings.

Abstract: In an internal clock signal generation circuit, a plurality of internal clock signals of different phases are generated based on an external clock signal. The internal clock signals are synchronized with the external clock signal by a PPL circuit. The plurality of internal clock signals are respectively supplied to a plurality of internal circuit blocks. Since the phases of the generated internal clock signals are different the phases of the internal clock signals arriving at the internal circuit blocks can be matched even if delays of the signals between the internal clock signal generation circuit and the plurality of internal circuit blocks are different. Thus, clock skews between the plurality of internal clock signals can be reduced and the phase of the internal clock signal and the phase of the external clock signal can be synchronized.

Abstract: A network communication device which can discard invalid packets at once is obtained. A plurality of cells received from input lines (IN#1-4) are stored in a shared buffer memory (SBM) and a control portion (CTL) manages tags and addresses. Among the received cells stored in the shared buffer memory (SBM), ones corresponding to discarded management data are not identified. Accordingly, virtually, the received cells in the shared buffer memory (SBM) can be discarded at once.

Abstract: Provided is a DLL circuit that can execute a precise delay synchronization operation without increasing the variable delay time range of a delay line. The DLL circuit comprises a phase comparator (3), a charge pump (6), an LPF (8) and a delay line (9), and operates to match phases of an input signal (CLKIN) and a feedback signal (FBCLK). The phase comparator (3) always outputs a phase comparison result that causes a delay time of the delay line (9) to increase, at the time of initial operation after a reset operation. The LPF (8) outputs a delay adjusting signal (S8) indicating that a delay time due to the delay line (9) becomes the minimum, in executing a reset.

Abstract: The operating speed of an apparatus which operates with a clock is increased by obtaining a clock having a constant duty ratio. The maximum variable delay quantity of a first variable delay circuit 11 is set more than one cycle and less than two cycles of an input clock IN. The delay quantities of the first and second variable delay circuits 11, 12 are decreased with a control signal Vin. In addition, the ratio of the delay quantity of the second variable delay circuit 12 to that of the first variable delay circuit 11 is set to a constant value which is less than 1. A control portion 13 increases and decreases the control signal Vin in such a manner that the phases of an input clock IN and an output clock OUT-A of the first variable delay circuit are coincident with each other. An output clock OUT of the device is set by the output clock OUT-A of the first variable delay circuit, and is reset by an output clock OUT-B of the second variable delay circuit.

Abstract: A voltage applying means applies a voltage which determines the logical value of a node to the node, with the signal at the node fixed. Then, an applied voltage removing means removes the voltage applied by the voltage applying means. First and second detecting means detects the logical value of the node before and after the voltage application and removal of the applied voltage. A judging means compares the results of detection of the first and second detecting means to judge whether or not the node is at a high impedance.

Abstract: It is an object to realize a synchronization circuit with small size and low consumption power which enables capturing and phasing of external data without running external clock in parallel. Internal clock (2) is delayed by a delay line (1) to produce delay clocks (3), and one of the delay clocks (3) having its rise almost corresponding to that of an external data signal (6) becomes a select clock (5). An elastic store circuit (7) is a circuit which controls a row of D-latches with a row of C elements. Thus the elastic store circuit (7) captures the external data signal (6) with enough set up hold time at timing of the select clock (5) and then outputs the captured external data as an internal data signal (8) in synchronization with the internal clock (2).

Abstract: A current type inverter circuit used in a Current Type Ring Oscillator and a Voltage-Controlled oscillator operates at a high speed with a low power consumption. A reference power source 1 has one end connected to a power source VDD and the other source receiving a reference current Iref. A drain and a gate of an NMOS transistor Q1 of a current mirror circuit CM1, as an input part, receive an input current Iin. A drain of an NMOS transistor Q2 is connected to an node N1 of the other end side of the reference power source 1 as an output part. As an input part, a drain and a gate of an NMOS transistor Q3 of a current mirror circuit CM2 are connected to the node N1 while a drain of an NMOS transistor Q4 functions as an output part for outputting an output current Iout. The transistors are set so that all of the conditions TS1.gtoreq.1, TS2.gtoreq.1 and TS1.multidot.