Abstract: A switch for digital communication networks includes a queuing system cape of implementing a broad class of scheduling algorithms for many different applications and purposes, with the queuing system including both a tag-based primary queue which contain ATM cells organized by priority and a secondary queue which contains ATM cells which are not yet scheduled for transmission and which are organized by virtual channel. A queuing decision module is provided to determine in which queue an incoming ATM cell should be deposited. A requeuing module operates when an event occurs that unblocks a particular virtual channel. The requeuing module, on occurrence of such an event, accesses the secondary queue to obtain another cell, to assign it priority and to move it to the primary queue. The queuing decision module, along with a virtual channel table, can be used easily to block virtual channels when necessary. The combination of queues also allows for round robin scheduling.

Abstract: Flows of data are controlled using an externally supplied clock. A clock-synchronized C-element C1 outputs a sending signal S1 of H level to a data latch DL1 and the subsequent clock-synchronized C-element C2 and outputs an acknowledge signal A1 of H level, in synchronization with a rise of a clock signal CLK1 which is inputted to the clock-synchronized C-element C1 after the clock-synchronized C-element C1 receives a sending signal S0 of H level. Following this, the clock-synchronized C-element C1 causes the acknowledge signal A1 to fall by the next rise of the clock signal CLK1. This latches the data latch DL1. A clock signal CLK2 rises before the clock signal CLK1 falls and rises once again. In synchronization with this rise, the clock-synchronized C-element C2 performs a similar operation. As a result, the precedent clock-synchronized C-element C1 causes the sending signal S1 to fall.

Abstract: In an internal clock signal generation circuit, a plurality of internal clock signals of different phases are generated based on an external clock signal. The internal clock signals are synchronized with the external clock signal by a PPL circuit. The plurality of internal clock signals are respectively supplied to a plurality of internal circuit blocks. Since the phases of the generated internal clock signals are different the phases of the internal clock signals arriving at the internal circuit blocks can be matched even if delays of the signals between the internal clock signal generation circuit and the plurality of internal circuit blocks are different. Thus, clock skews between the plurality of internal clock signals can be reduced and the phase of the internal clock signal and the phase of the external clock signal can be synchronized.

Abstract: A purpose of this invention is to realize a bus system of high speed and low power consumption type applying precharge. A precharge signal input line (4), a power source potential (V.sub.DD), and a bus (1) are connected to a gate electrode, a drain region, and a source region of a first MOS transistor (MNP), the power source potential (V.sub.DD), a node (N1), and the bus (1) are connected to a gate electrode, a drain region, and a source region of a second MOS transistor (MN1), and the precharge signal input line (4) through an inverter (3), the power source potential (V.sub.DD), and the node (N1) are connected to a gate electrode, a source region, and a drain region of a third MOS transistor (MP1), respectively. In precharge period (PC=H), the potential of the bus (BUS) rises gradually, and the both transistors (MNP, MN1) are turned off. In EVL period (PC=L), when data is output from a register (6), the potential of the bus (BUS) drops, and the second MOS transistor (MN1) is turned on.

Abstract: A current type inverter circuit or the like is obtained which operates at a high speed with a low power consumption. A reference power source 1 has one end connected to a power source VDD and the other source receiving a reference current Iref. A drain and a gate of an NMOS transistor Q1 of a current mirror circuit CM1, as an input part, receive an input current Iin. A drain of an NMOS transistor Q2 is connected to an node N1 of the other end side of the reference power source 1 as an output part. As an input part, a drain and a gate of an NMOS transistor Q3 of a current mirror circuit CM2 are connected to the node N1 while a drain of an NMOS transistor Q4 functions as an output part for outputting an output current Iout. The transistors are set so that all of the conditions TS1.gtoreq.1, TS2.gtoreq.1 and TS1.multidot.

Abstract: A plurality of shift memories shifting data are connected in series, destination indicating bits indicative of data destination are stored in destination indicating bit memories corresponding to the shift memories respectively, and a searching circuit is provided adjacent to each of the destination indicating bit memories, which searching circuit searches data by searching the destination indicating bits.

Abstract: A VCO circuit 4 of a PLL circuit 1 includes M delay time variable inverters 5.1 to 5.M which are connected in a ring shape. Load driving capability of delay time variable inverters 5.1 to 5.M is increased gradually toward output node OUT which is connected directly to load capacity CL. Accordingly, a high load driving capability is obtained without provision of a separate buffer.

Abstract: An input signal is inverted by an inverter in the first stage and an n-channel MOS transistor on the pull up side in a driver is driven, while an output signal of the inverter in the first stage is inverted by an inverter in the next stage and an n-channel MOS transistor on the pull down side is driven. A driving signal is output from a connection point between the n-channel MOS transistor on the pull up side and the n-channel MOS transistor on the pull down side, and an output transistor is driven by the driving signal. Since a gate voltage of the output transistor increases only by a value of a power supply voltage Vdd minus threshold voltage V.sub.T, a rise time and a fall time of a gate potential can be reduced, resulting in improvement in the duty cycle.

Abstract: It is an object of the present invention to provide a phase comparator which can compare phase at high speed with simple structure. The phase is compared by a precharge type NAND gate including transistors (Q35-Q37). The result of comparison in the NAND gate is then outputted only in a period in which the input clock CLKref is at "1" by the NAND gate (NA 15), and thus the phase lag of the internal clock CLKint with respect to the input clock CLKref is detected. Phase lead of the internal clock CLKint with respect to the input clock CLKref is compared with interchanged relation of clocks inputted to a phase detecting portion (PD 2). Phase comparison can be made at high speed with a simple circuit including the precharge type NAND gate and the NAND gate (NA 15).

Abstract: Jitter provided from a phase locked loop circuit is extracted by pulse extracting circuits. Determination is made by a counter whether a pulse signal representing the jitter reaches a predetermined number within a predetermined time period. An evaluation signal representing the level of the jitter is provided from a thermometer decoder according to the determination result.

Abstract: In order to obtain a buffer control shift register for an ATM switching unit for transmitting ATM cells which are stored in the unit while controlling the same in response to deadlines thereof, the unit comprises a comparator (53) for comparing dispatch times DPT.sub.0 of inputted ATM cells with those stored in a register (51). Registers (50, 51) are formed to be capable of bidirectional shifting (positive and negative directions along .gamma.). A shift/write control (54) rearwardly shifts data having a larger dispatch time in response to the result of comparison of the comparator (53), to write data of the inputted ATM cells in the vacated portion. It is possible to sequence data of the shift register from the frontmost stage in order of the dispatch times.

Abstract: A data queuing apparatus processes data switching and queuing using a smaller capacity memory, while reducing data discard and loss possibility. Received limited-length data at the input line is written in shift memories, which can shift the data to the next stage regardless of the destination of the data. Destination indicating bits, which indicate the destination of the data, are associated with each of shift memories. A search circuit detects an asserted bit among the destination indicating bits corresponding to the output lines. The data is extracted by a selector. Then the selector transmits the data to the desired output line, and the data stored in the previous stage of the shift memory is shifted. The memory is used in common with a plurality of output lines, so that a lower possibility of data discard and loss can be attained in a smaller capacity memory.

Abstract: A crosspoint LSI adapted to an exchanger in ISDN, for transmission of asynchronous transfer mode (ATM) cells in communication is provided. The crosspoint switching LSI includes many unit switch cells arranged in rows and columns. When a unit switch cell is turned on, the unit switch cell responds to a differential data signal on an input data line to drive differentially an output data line pair. The unit switch cells operate differentially so that the data signals of the ATM cells are transmitted, which improves a signal transmission rate.

Abstract: The output circuit according to the present invention includes a bipolar transistor (Q.sub.1), a resistance (R.sub.1) and a constant current source. The transistor (Q.sub.1) has its collector connected to a power supply node (V.sub.CC), its emitter connected to an output node (Do), and its base connected to the other end of the resistance (R.sub.1). The resistance (R.sub.1) has one end connected to the power supply node (V.sub.CC). The constant current source is connected between a power supply node (V.sub.EE) and the base of the transistor (Q.sub.1) and is turned on/off in response to an input signal (IN) to generate a current (I.sub.1) for bringing output into a low level only in the on state. The constant current source does not generate the current (I.sub.1) at the time of output of a high level, and causes the current (I.sub.1) to flow through the resistance (R.sub.1) only at the time of output of a low level. As a result, power consumption can be reduced.

Abstract: A semiconductor integrated circuit serves as an interface between a CPU and the outside enabling communication between systems. More specifically, when a selector is switched to the CPU side, RAMs are accessed at random by the CPU to write data therein, and when the selector is switched to transmission controlling portion, the RAMs are serially accessed by the transmission controlling portion to read data therefrom to be transmitted. When selectors are switched to a reception controlling portion side, RAMs are serially accessed by the reception controlling portion to write data therein, and when the selectors are switched to the CPU side, the RAMs are accessed at random by the CPU to read data therefrom.

Abstract: A BiMOS amplifier device includes one stage which can function as both a level-shift and buffer stage and an amplifier stage. The amplifier includes first and second bipolar transistors having their bases connected to first and second input terminals, respectively, having their collectors connected to a point of first potential, and having their emitters connected to the sources of first and second MOS transistors, respectively. The drains of the first and second MOS transistors are connected through respective impedance means to a point of second potential. The gate of each of the MOS transistors is connected to the drain of the other MOS transistor. An output terminal is connected to the drain of at least one of the MOS transistors.

Abstract: Incoming lines (I0 to I7) are connected to a space switch (2) through input data latches (1). The space switch (2) is connected to a normal/test changeover switch (12), which is connected to a normal/test changeover switch (13) through serial-to-parallel converting circuits (3), common buffer memories (4) and parallel-to-serial converting circuits (5). Space switches (6) are connected to the normal/test changeover switch (13). Outgoing lines (O0 to O7) are connected to the space switches 6 through output data latches (8). Connection states in the switches (2, 6) are placed in transposed relation to each other by a transposed connection generating circuit (10) in a test operation, so that the switches (2, 6) are directly connected to each other through the switches (12, 13). Predetermined data applied to the incoming lines are intactly used as expected values for judgement of the normal or abnormal operation of the set of switches of matrix structure.

Abstract: A PLL circuit apparatus in accordance with the present invention includes a phase comparator, a delay circuit, a NOR circuit, and a loop filter. The phase comparator detects a phase difference between a reference clock signal and an internal clock signal. The delay circuit delays the reference clock signal by a delay time of an output of the phase comparator. The NOR circuit determines which pulse width is larger of a phase difference detecting signal from the phase comparator or of the delayed reference clock signal. The loop filter has its gain changed in response to an output of the NOR circuit. Thus, it is possible to shorten a synchronization pull-in time and accurately detect a deviation in synchronization. In addition, if a gain control signal is reset on the basis of logic states of a reference clock signal and an internal clock signal in accordance with rising edges and falling edges of the clock signals, it is possible to generate successive gain control signals.

Abstract: A ratio latch included in each slave latch is formed of a tri-state inverter and a weak inverter. During a period when a parallel input signal is supplied to the ratio latch in each master latch in response to a trigger clock signal, the tri-state inverter attains a high impedance state in response to an inverted trigger clock signal.

Abstract: An output circuit 1 comprises a constant current source 11, a switch 12, and an output pad 14. The switch 12 is connected between the constant current source 11 and the output pad 14. A transmission path 3 is connected to the output pad 14. The transmission path 3 is coupled to a terminator voltage V.sub.TT by a resistor for pull up. Reflection of a signal or generation of noise can be suppressed by bringing the resistance value of the resistor 4 close to a characteristic impedance of the transmission path 3. A voltage amplitude on the transmission path 3 can be determined arbitrarily by adjusting current value of the constant current source 11 and resistance value of the resistor 4.